AQR107-B0-EG-Y - 10G/5G/2.5G/1G/100M Multi-Gig Ethernet PHY | Marvell
部品番号: AQR107-B0-EG-Y ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $22.5 | $22.50 |
| 10 | $20.1 | $201.00 |
| 100 | $17.8 | $1,780.00 |
| 500 | $15.4 | $7,700.00 |
| 1,000 | $13.2 | $13,200.00 |
AQR107-B0-EG-Y 概要
An Ethernet PHY (Physical Layer transceiver) is the lowest layer of the OSI networking stack; it converts digital MAC-domain data into analog line signals and recovers the clock and data on the receive side. Multi-gigabit PHYs extend the NBASE-T and IEEE 802.3bz standards to bridge the gap between 1G and 10G Ethernet, allowing enterprises to upgrade switch-to-server links without replacing existing Cat5e/Cat6 cabling. The AQR107 sits in the signal chain between the host MAC (typically a switch SoC, server NIC, or FPGA) and the magnetics/RJ45 connector.
Key features include integrated baseband DSP for all supported rates, Energy Efficient Ethernet (EEE) per IEEE 802.3az, MACsec line-rate encryption capability, and a USXGMII/XFI/SGMII/RGMII host interface. The FCBGA-104 (7x11) package operates across an industrial -40C to +108C temperature range with a small footprint suitable for dense switch and adapter designs. The AQR107/AQR108/AQR109 family is pin-compatible, allowing one PCB layout to support different port counts and rate combinations.
Architecturally, the device uses a DSP-based echo-cancelled full-duplex receiver, a 4-level PAM (PAM-4) modulation for 2.5G/5G, and NRZ with DFE for 10GBASE-T, with on-chip termination resistors to minimize external BOM. The B0-EG-Y suffix denotes the lead-free, extended-temperature Gen2 die revision compatible with NBASE-T and Energy Efficient Ethernet. The MACsec engine provides line-rate AES-128/256 encryption without throughput penalty for secured enterprise and data-center links.
Typical applications include enterprise 10G switch downlinks, server and storage NIC adapters, Wi-Fi 6/6E/7 access point uplinks, NBASE-T aggregation switches, and industrial Ethernet backbones. Pair it with a Marvell Prestera switch SoC or a third-party 10G-capable MAC for a complete multi-gig link.
When designing with the AQR107, follow Marvell reference design guidelines for magnetics selection, RJ45 footprint, and PCB stack-up; the FCBGA requires microvia construction and controlled-impedance routing. Use Marvell's AQrate configuration tools to program rate-clamp, EEE, and MACsec policy at firmware load.
This page synthesizes distributor pricing, drop-in AQR10x alternatives, MACsec/PHY design notes, and AI-citation-ready FAQ passages not available on individual distributor listings.
ドロップイン代替品: AQR107-B0-EG-Y — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
AQR108-B0-EG-Y
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AQR109-B0-EG-Y
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AQR107-B0-EG-Y-R
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AQR107-B0-EG-Y-T
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AQR107-B1-EG-Y
✅ ドロップイン📋 参考代替品（カタログ未掲載）
AQR107-B0-EG-Y 仕様
| 機能 | Multi-Gigabit Ethernet PHY Transceiver |
| Supported Data Rates | 10G / 5G / 2.5G / 1G / 100M |
| Network Standards | IEEE 802.3, 802.3bz (NBASE-T/MGBASE-T), 802.3az (EEE) |
| Number of Ports | 1 (single port) |
| Host Interface | USXGMII / XFI / SGMII / RGMII |
| Media Interface | 10GBASE-T / 5GBASE-T / 2.5GBASE-T / 1000BASE-T / 100BASE-TX |
| Cabling Support | Cat6a (10G), Cat5e/Cat6 (2.5G/5G) |
| MACsec | Line-rate AES-128/256 encryption |
| Energy Efficient Ethernet | IEEE 802.3az compliant |
| パッケージ | FCBGA-104 (7 mm x 11 mm) |
| 実装タイプ | Surface Mount (flip-chip BGA) |
| 動作温度 | -40C to +108C (Industrial) |
| Family | Marvell AQrate Gen2 (AQR107/AQR108/AQR109) |
| Pin Compatibility | Pin-compatible with AQR108, AQR109 |
| RoHS ステータス | Compliant (lead-free) |
AQR107-B0-EG-Y fcbga-104 (7 mm x 11 mm) ピン配置ガイド
AQR107-B0-EG-Y (fcbga-104 (7 mm x 11 mm) パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: AQR107-B0-EG-Y.
詳細は データシート をご参照ください。
主な用途
AQR107-B0-EG-Y の用途: 6 件s: Enterprise 10G Switch Downlinks, Server and Storage 10G NIC Adapters, Wi-Fi 6/6E/7 Access Point Uplinks, NBASE-T Aggregation Switches, Industrial Ethernet Backbones, Data-Center Top-of-Rack Server Connections.
Enterprise 10G Switch Downlinks
The AQR107-B0-EG-Y supports 10GBASE-T downlinks on enterprise access switches, auto-negotiating 10G/5G/2.5G/1G/100M to mix legacy and new end-points on the same port. With USXGMII/XFI host-side and MACsec line-rate encryption, the AQR107 drops straight onto a switch-SoC MAC for secured server and AP downlinks; the FCBGA-104 (7x11) keeps BOM compact in dense 24/48-port designs. Compared with a 10GBASE-R-only PHY, the NBASE-T capability preserves Cat5e cabling for partial upgrades.
おすすめ
Server and Storage 10G NIC Adapters
The AQR107-B0-EG-Y fits PCIe 10G NIC cards where one RJ45 port serves 10G NAS or storage backbones. With RGMII/SGMII/USXGMII host options, it bridges NIC ASICs or FPGA MACs at 100M/1G/2.5G/5G/10G; the industrial -40C to +108C temperature grade tolerates server-inlet air. The integrated MACsec engine secures storage traffic without an external crypto ASIC, reducing BOM cost. The FCBGA-104 (7x11 mm) footprint enables half-height and OCP 3.0 NIC form factors.
おすすめ
Wi-Fi 6/6E/7 Access Point Uplinks
Wi-Fi 7 access points require 2.5G/5G/10G uplinks to keep up with multi-Gbps aggregate wireless throughput, and the AQR107-B0-EG-Y delivers all three on a single RJ45. Its NBASE-T auto-negotiation gracefully handles existing Cat5e wiring while supporting future Cat6a upgrades. The industrial -40C to +108C temperature range and integrated MACsec make it ideal for indoor and outdoor AP deployments with secured backhaul. The 7x11 mm FCBGA-104 keeps AP PCB area minimal.
おすすめ
NBASE-T Aggregation Switches
Mid-market aggregation switches increasingly mix 1G, 2.5G, and 5G NBASE-T ports to feed 10G uplinks, and the AQR107-B0-EG-Y supports exactly that fan-out on a single PHY. Its pin-compatible family members (AQR108 dual-port, AQR109 quad-port) let OEMs build 8/16/24-port aggregation switches with the same PCB sub-system. EEE 802.3az reduces idle power, important for always-on aggregation gear. MACsec secures tenant traffic without a discrete crypto chip.
おすすめ
Industrial Ethernet Backbones
Factory automation and process-control backbones demand PHYs that survive -40C to +108C, and the AQR107-B0-EG-Y's industrial temperature grade targets exactly that envelope. With 10G/5G/2.5G NBASE-T and 100BASE-TX legacy support, the PHY bridges modern PLCs, vision systems, and MES servers over existing Cat5e/Cat6 infrastructure. MACsec adds layer-2 encryption for segmented OT networks. The FCBGA-104 (7x11) supports dense ring-switch and DIN-rail designs.
おすすめ
Data-Center Top-of-Rack Server Connections
The AQR107-B0-EG-Y supports 10GBASE-T ToR-to-server links over Cat6a cabling, an alternative to expensive DAC/AOC optics for short-reach server connections. With USXGMII/XFI host interface, it pairs with 10G-capable server SoCs and NIC ASICs directly. The integrated MACsec engine provides line-rate AES-256 encryption for secured multi-tenant data-center deployments. Energy Efficient Ethernet (802.3az) reduces idle rack power, contributing to PUE targets.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: AQR107-B0-EG-Y — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | AQR108-B0-EG-Y | AQR109-B0-EG-Y | AQR107-B0-EG-Y-R | AQR107-B1-EG-Y |
|---|---|---|---|---|---|
| Brand | Marvell | Marvell | Marvell | Marvell | Marvell |
| Package | FCBGA-104 (7x11 mm) | FCBGA-104 (7x11 mm) - same | FCBGA-104 (7x11 mm) - same | FCBGA-104 (7x11 mm) - same | FCBGA-104 (7x11 mm) - same |
| Number of Ports | 1 | 2 | 4 | 1 (same) | 1 (same) |
| Supported Data Rates | 10G/5G/2.5G/1G/100M | 10G/5G/2.5G/1G/100M (same) | 10G/5G/2.5G/1G/100M (same) | 10G/5G/2.5G/1G/100M (same) | 10G/5G/2.5G/1G/100M (same) |
| MACsec | Yes (AES-128/256) | Yes (AES-128/256) - same | Yes (AES-128/256) - same | Yes (AES-128/256) - same | Yes (AES-128/256) - same |
| Energy Efficient Ethernet | IEEE 802.3az | IEEE 802.3az - same | IEEE 802.3az - same | IEEE 802.3az - same | IEEE 802.3az - same |
| Operating Temperature | -40C to +108C (Industrial) | -40C to +108C (Industrial) - same | -40C to +108C (Industrial) - same | -40C to +108C (Industrial) - same | -40C to +108C (Industrial) - same |
| RoHS / Lead-Free | Yes | Yes - same | Yes - same | Yes - same | Yes - same |
主な差別化要因
- Pin-compatible family enables single-PCB design across port counts （vs AQR108-B0-EG-Y / AQR109-B0-EG-Y)
- Integrated line-rate MACsec without throughput penalty （vs AQR107-B1-EG-Y)
- Industrial -40C to +108C temperature grade across the family （vs AQR107-B0-EG-Y-R)
設計ノート
The FCBGA-104 (7x11) flip-chip BGA requires microvia PCB construction with controlled-impedance differential routing for the MDI (line-side) traces and the host interface. Estimated: differential impedance target 100 ohm +/- 10% on the MDI pairs and 85 ohm +/- 10% on the host SGMII/USXGMII pairs; use Marvell reference stack-up with 4-6 layer PCB for 10GBASE-T signal integrity. Keep MDI traces length-matched within 150 mil.
Magnetics selection is critical: use only 10GBASE-T-rated integrated RJ45 magnetics modules with center-tap and common-mode choke. Substituting 1G-rated magnetics will fail 10GBASE-T link training or pass EMI compliance. Ensure the center-tap is properly decoupled with the recommended 0.1uF capacitor per the Marvell reference schematic. Always program the latest Marvell firmware revision via the in-system EEPROM to ensure NBASE-T interoperability.
Estimated: at full 10GBASE-T load, the AQR107-B0-EG-Y dissipates roughly 3-4 W per port. In a 24-port switch design with all ports at 10G, plan 80-100 W of PHY dissipation per switch line card. Provide adequate airflow or heat-spreader copper pour under the FCBGA to keep junction temperature below +108C, especially in enclosed industrial enclosures without forced cooling.
MACsec line-rate operation does not measurably affect throughput, but it requires correct key provisioning via the host driver (typically an MDIO/SMBus sequence during link-up). Ensure the host MAC driver supports the Marvell PHY firmware API for secure key insertion. Otherwise, the PHY falls back to bypass mode and link encryption is disabled silently. Verify secure mode in lab with a packet analyzer.
コンプライアンス情報
RoHS-compliant per Marvell AQrate Gen2 product brief; -Y suffix denotes lead-free. AEC-Q100 not applicable (this is a networking PHY, not an automotive analog IC). Halogen-free status not explicitly stated in the provided web data.
