BCM8156FBIFB - 11.35 Gbps Ethernet Transceiver IC | Broadcom
部品番号: BCM8156FBIFB ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $42.5 | $425.00 |
| 100 | $39.8 | $3,980.00 |
| 500 | $36.5 | $18,250.00 |
| 1,000 | $33.2 | $33,200.00 |
BCM8156FBIFB 概要
A transceiver (Tx/Rx) is an interface IC that converts parallel digital data into a serial differential signal for transmission over copper backplanes, cables, or optical modules, and performs the reverse conversion on the receive side. Transceivers sit within the broader category hierarchy of interface ICs -> wired communication ICs -> Ethernet transceivers -> serial transceivers -> semiconductor devices. They are foundational building blocks in the PHY (physical layer) of the OSI model, where they implement PCS, PMA and PMD sublayers per IEEE 802.3 standards, working with MAC controllers and clock-and-data recovery circuits.
Key features include multi-rate operation up to 11.35 Gbps, integrated serializer/deserializer (SerDes) functionality, adaptive equalization for lossy channels, and low-latency data path design. The BCM8156 family targets backplane and chip-to-chip interconnect applications where signal integrity at multi-gigabit rates is critical.
The BCM8156FBIFB integrates high-speed analog front ends with digital logic to handle pre-emphasis, receive equalization, and clock data recovery on each lane. Its adaptive equalization engine compensates for frequency-dependent loss in FR-4 backplanes and improves eye opening at the receiver.
Typical applications include 10G/40G Ethernet switches, optical transport network (OTN) equipment, high-speed router line cards, data center fabric interconnects, and backplane serializer/deserializer links.
When designing with this device, ensure proper PCB layout for high-speed serial channels, including controlled-impedance differential routing (typically 100 ohm differential), continuous reference planes, and AC-coupling capacitors on each lane. The FBIFB designator indicates a specific package/reel variant.
ドロップイン代替品: BCM8156FBIFB — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: BCM8156FBIFB （同一形状・フットプリント） — 相違点: Function, Product Type, Protocol.
クイック比較ツール — 並列比較する代替部品を選択:
BCM8155FBIFB
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM8154FBIFB
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM8727
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM8074
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
88X5113-A1-BVW4C000
✅ ドロップイン✓ 在庫あり
$9.5 / 個
データシートを見る →IN112010
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM8156FBIFB 最大定格＆電気的特性
| Product Type | Ethernet Transceiver IC |
| Manufacturer | Broadcom Limited (formerly Avago) |
| 機能 | Transceiver - Ethernet |
| Maximum Data Rate | 11.35 Gbps |
| Protocol | Ethernet |
| Package Type | Surface Mount (FBIFB designator) |
| 実装タイプ | Surface Mount |
| ライフサイクル状態 | Obsolete per Ersa Electronics listing |
BCM8156FBIFB surface mount (fbifb designator) ピン配置ガイド
BCM8156FBIFB (surface mount (fbifb designator) パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: BCM8156FBIFB.
詳細は データシート をご参照ください。
主な用途
BCM8156FBIFB の用途: 6 件s: 10G Ethernet Switch Line Cards, OTN (Optical Transport Network) Equipment, High-Speed Router Line Cards, Data Center Fabric Interconnects, Backplane Serializer/Deserializer Links, High-Speed Test and Measurement Equipment.
10G Ethernet Switch Line Cards
The BCM8156FBIFB's 11.35 Gbps SerDes line rate maps directly to 10 Gigabit Ethernet (10GbE) and 10G KR backplane applications, making it a natural PHY choice for top-of-rack and chassis-based 10G switches. Placed between the MAC/FPGA and the SFP+ cage or backplane connector, the transceiver performs PCS/PMA encoding/decoding plus adaptive receive equalization to compensate for FR-4 channel loss. Unlike lower-rate 1G/2.5G PHYs, the BCM8156 handles the full 10.3125 Gbps line rate plus encoding overhead, supporting both 10GBASE-KR backplane and 10GBASE-SR/LR optical modules when paired with appropriate optical front ends.
おすすめ
OTN (Optical Transport Network) Equipment
The 11.35 Gbps line rate of the BCM8156FBIFB makes it suitable for OTU2 (Optical Transport Unit 2) interfaces per ITU-T G.709, which carry 10 Gbps of payload plus forward-error-correction and framing overhead. In OTN muxponder and cross-connect equipment, the BCM8156 serves as the PHY between the OTN framer ASIC and the line-side optics or tunable laser driver. Compared to native 10GbE-only transceivers, the BCM8156 supports the OTU2 bit rate that enables OTN transport of Ethernet, SONET/SDH, or storage payloads with full performance monitoring.
おすすめ
High-Speed Router Line Cards
In carrier-grade routers and aggregation switches, the BCM8156FBIFB delivers the multi-gigabit SerDes function for distributing traffic across backplane midplanes between line cards and switch fabric cards. The 11.35 Gbps lane rate scales to 40G (4×80) and 100G (10×80) aggregate port bandwidths via multiple BCM8156 devices. Compared with legacy 3.125 Gbps SerDes, the BCM8156's adaptive equalization recovers signal integrity across longer backplane channels, reducing the need for external retimers and lowering BOM cost in chassis-based router designs.
おすすめ
Data Center Fabric Interconnects
The BCM8156FBIFB supports the 10G/11.35 Gbps lane rate commonly used in data center top-of-rack (ToR) and leaf-spine fabric interconnects. Used at the PHY layer between switching ASICs and SFP+ optical modules or direct-attach copper (DAC) cables, it enables 10GbE server connections and aggregation uplinks. The integrated adaptive receive equalization compensates for the frequency-dependent loss of standard FR-4 PCB traces used in commodity server motherboards, eliminating external retimers in moderate-reach (under 1m) applications.
おすすめ
Backplane Serializer/Deserializer Links
The BCM8156FBIFB functions as a multi-lane SerDes for proprietary or standards-based backplane interconnects in chassis systems such as ATCA, advanced switching platforms, and telecom equipment racks. Per channel, it serializes parallel data for transmission across the backplane and deserializes received data with clock-data recovery, eye-opening monitoring, and adaptive equalization. Compared to optical interconnect solutions, backplane SerDes links using the BCM8156 reduce cost and power per gigabit of bandwidth while delivering adequate reach for in-chassis applications.
おすすめ
High-Speed Test and Measurement Equipment
In high-speed test equipment such as BERT (Bit Error Rate Tester), protocol exercisers, and signal integrity analyzers, the BCM8156FBIFB provides the high-speed serial interface for generating and receiving test patterns at 10G-class line rates. The transceiver's adaptive equalization and signal-conditioning features allow test equipment to emulate real-world lossy channels. Compared with discrete SerDes FPGA IP, the BCM8156 offers proven performance and a documented register map, accelerating firmware development for production test systems.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: BCM8156FBIFB — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | BCM8155FBIFB | BCM8154FBIFB | BCM8727 | 88X5113-A1-BVW4C000 |
|---|---|---|---|---|---|
| Package | Surface Mount (FBIFB) | Surface Mount (FBIFB) | Surface Mount (FBIFB) | Surface Mount | Surface Mount |
| Brand | Broadcom | Broadcom | Broadcom | Broadcom | Marvell |
| Protocol | Ethernet | Ethernet | Ethernet | Ethernet / OTN | Ethernet |
| Function | Transceiver | Transceiver | Transceiver | Transceiver | Transceiver |
| Adaptive Equalization | Yes (per Ersa listing) | Yes | Yes | Yes | Yes |
| Application Domain | 10G Ethernet, Backplane | Lower-rate Ethernet | Lower-rate Ethernet | 10G Ethernet, OTN | 10G Ethernet, Routing |
主な差別化要因
- Higher 11.35 Gbps line rate supports OTU2 OTN plus 10GbE （vs BCM8155FBIFB)
- Broadcom-proven SerDes architecture （vs 88X5113-A1-BVW4C000)
- Integrated adaptive receive equalization for FR-4 channels （vs BCM8154FBIFB)
設計ノート
For BCM8156FBIFB designs targeting 11.35 Gbps line rates, use 100-ohm differential impedance-controlled stripline or microstrip routing with continuous reference planes on adjacent layers. Place AC-coupling capacitors (typically 100 nF X7R) within 200 mils of the IC transmit pins. Avoid 90-degree bends; use gentle curves or 45-degree mitered corners. Isolate high-speed lanes from noisy power and clock traces with at least 4W-50 spacing.
Differential pair length matching is critical: match intra-petal lane lengths within 5 mils (0.127 mm) at 11.35 Gbps to meet the 0.2 UI unit interval budget at the receiver. Use ground vias as a return-current stitch every lambda/10 along the trace. The SerDes reference clock input should be routed with the same 100-ohm differential discipline and isolated from data lanes to minimize jitter coupling.
Estimated: at typical operating conditions for a multi-lane 11.35 Gbps transceiver, expect per-lane power around 200-300 mW, so a quad-lane design consumes 800 mW-1.2 W. Use a star-ground topology to isolate analog PLL supply pins from digital logic supply; decouple each supply pin with 100 nF X7R plus 10 uF bulk ceramic. Estimated values are based on typical Broadcom SerDes families; consult the manufacturer datasheet for definitive current per rail.
コンプライアンス情報
Compliance fields unknown because the verified distributor listings do not include explicit RoHS, REACH, or AEC-Q100 declarations for this obsolete Broadcom part; consult Broadcom's PCN documentation for definitive compliance status.
