BCM84894B0IFSBG - Quad-Port Multi-Rate Ethernet PHY | Broadcom
部品番号: BCM84894B0IFSBG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $268 | $2,680.00 |
| 100 | $245 | $24,500.00 |
| 500 | $222 | $111,000.00 |
| 1,000 | $205 | $205,000.00 |
BCM84894B0IFSBG 概要
An Ethernet PHY (physical layer transceiver) is the analog/digital interface between the MAC layer of a switch or NIC and the copper or optical cable medium. Multi-rate PHYs unify multiple line rates on a single port to simplify board layout, reduce BOM cost, and support heterogeneous speeds across modern data center fabrics. The BCM84894 sits in the taxonomy: Ethernet PHY -> transceiver -> interface IC -> integrated circuit -> semiconductor.
Key features include integrated KR/CR backplane equalization with adaptive DFE/FFE, IEEE 802.3bj/bm/bs/an compliance, low-latency PCS/PMA architecture, and per-port diagnostic eye-monitor capability. The FBGA package integrates the PHY with PMD sublayers, supporting both gearbox and gearbox-less MAC attachments through a flexible SERDES interface. Each port independently negotiates between 10G, 25G, and 100G, allowing mixed-speed backplanes without firmware rework.
The architecture uses a DSP-based receiver with continuous-time linear equalizer (CTLE), decision-feedback equalizer (DFE), and feed-forward equalizer (FFE) to compensate for channel loss up to 30+ dB at Nyquist. On the line side, a low-jitter PLL and voltage-mode driver maintain IEEE 802.3-compliant transmit signal integrity across long backplanes and DAC cables up to 5 meters.
Typical applications include 100G/25G ToR data center switches, hyperscale leaf-spine fabrics, high-performance network interface cards (NICs), and Ethernet-based storage front-ends. The quad-port density also makes it well-suited for QSFP28-based modular line cards requiring four lanes per cage.
When designing with this PHY, verify MAC-side SerDes rate compatibility and PCB channel loss budget against the 802.3bj KR/CR specification. Adequate thermal relief is essential: a quad-port device driving 100G per port can dissipate several watts, requiring thermal vias under the FBGA and airflow management in the chassis.
This page synthesizes distributor pricing, drop-in alternative availability, and application context drawn from Broadcom marketing materials - engineering guidance not found in the manufacturer datasheet alone.
ドロップイン代替品: BCM84894B0IFSBG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
BCM84891B0IFSBG
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM84848B0IFSBG
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM84894B0IFSBG-EVB
✅ ドロップイン📋 参考代替品（カタログ未掲載）
BCM84894A0IFSBG
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM84894B1IFSBG
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
BCM84894B0IFSBG 最大定格＆電気的特性
| 機能 | Quad-Port Multi-Rate Ethernet PHY Transceiver |
| Supported Data Rates | 10G / 25G / 100G per port |
| Ethernet Standards | IEEE 802.3bj, 802.3bm, 802.3bs, 802.3by, 802.3an (auto-negotiation) |
| インターフェースタイプ | Backplane KR / Direct-Attach Copper CR |
| Number of Ports | 4 |
| Package Type | FBGA |
| 実装タイプ | Surface Mount |
| MAC Interface | SERDES (KR/CR-capable PCS/PMA) |
| Signal Conditioning | Adaptive CTLE / DFE / FFE |
| Reach | Backplane + DAC up to ~5 m (KR/CR) |
| Compliance | RoHS per Broadcom product page |
| Lifecycle | Active production |
| Manufacturer | Broadcom Inc. |
BCM84894B0IFSBG fbga ピン配置ガイド
BCM84894B0IFSBG (fbga パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: BCM84894B0IFSBG.
詳細は データシート をご参照ください。
主な用途
BCM84894B0IFSBG の用途: 6 件s: 100G/25G Top-of-Rack Data Center Switch, Hyperscale Leaf-Spine Network Fabric, High-Performance Network Interface Card (NIC), 5G Telco Backhaul and Midhaul Equipment, Ethernet Storage Fabric (NVMe-oF / iSCSI), High-Frequency Trading / Low-Latency Networks.
100G/25G Top-of-Rack Data Center Switch
The BCM84894B0IFSBG is a natural fit for top-of-rack (ToR) data center switch line cards where each port can independently operate at 10G, 25G, or 100GBASE-KR/CR. Its quad-port density enables a QSFP28 cage per port with mixed-speed uplink and downlink capability, eliminating the need for separate 25G and 100G PHY silicon. Per-port auto-negotiation across the 802.3bj/bm/bs/by family lets the same hardware serve 25G server access today and migrate to 100G servers without board redesign. The integrated CTLE/DFE/FFE compensation supports backplane traces up to ~5 m of DAC cable, which matches typical ToR-to-leaf cable lengths.
おすすめ
Hyperscale Leaf-Spine Network Fabric
In hyperscale leaf-spine fabrics where every port runs 100G, the BCM84894B0IFSBG's 100GBASE-KR4/CR4 capability per port delivers four 100G links per device, enabling compact 32x100G or 64x100G line cards. Its low-latency PCS/PMA architecture preserves cut-through switching latency budgets that hyperscale operators depend on for east-west traffic patterns. Adaptive equalization copes with the long, lossy backplanes typical of 1U-2U chassis designs. Combined with Broadcom's StrataXGS or Tomahawk switch silicon, the BCM84894 family powers some of the largest cloud-provider fabrics in production today.
おすすめ
High-Performance Network Interface Card (NIC)
Dual- and quad-port 25G/100G NICs use the BCM84894B0IFSBG as the line-side PHY to interface between the NIC controller ASIC and QSFP28 cages. The quad-port density supports a 4x25G or 1x100G configuration in a single PHY, reducing board area and BOM cost versus discrete single-port PHYs. Adaptive KR/CR signal conditioning handles both backplane mid-planes and direct-attach copper (DAC) cables used in server-to-TOR connections. Integrated IEEE 1588v2 timestamping supports financial-trading and telco workloads that require sub-microsecond synchronization across NIC populations.
おすすめ
5G Telco Backhaul and Midhaul Equipment
5G mobile infrastructure requires deterministic, low-latency Ethernet for backhaul and midhaul links between radio units, distributed units, and centralized units. The BCM84894B0IFSBG's 25G/100G KR/CR support plus IEEE 1588v2 timestamping meets the synchronization accuracy required by 3GPP timing specifications. Its per-port auto-negotiation enables a single line card to serve mixed 10G/25G CPRI/eCPRI traffic alongside 100G operator traffic. The device's industrial temperature tolerance (per Broadcom datasheet) supports outdoor-cabinet deployments typical of telco aggregation sites.
おすすめ
Ethernet Storage Fabric (NVMe-oF / iSCSI)
High-performance Ethernet storage fabrics such as NVMe-over-Fabrics (NVMe-oF) and iSCSI run over 25G/100G KR/CR links, where the BCM84894B0IFSBG provides the line-side physical layer. Its low-latency PCS/PMA path preserves the storage I/O latency budget that flash arrays demand for sub-100-microsecond access. The quad-port density supports 4x25G or 1x100G per storage controller port, enabling high-throughput storage target interfaces. Adaptive equalization across long backplanes and DAC cables is critical for hyperconverged storage rack deployments.
おすすめ
High-Frequency Trading / Low-Latency Networks
High-frequency trading (HFT) and other latency-sensitive networks rely on deterministic cut-through switching with sub-microsecond PHY-layer latency. The BCM84894B0IFSBG's low-latency PCS/PMA architecture minimizes per-hop delay while still delivering full 25G/100G line-rate operation. IEEE 1588v2 timestamping provides the synchronization accuracy that regulated trading exchanges require for transaction timestamping. The device's adaptive equalization handles both intra-datacenter backplanes and inter-floor DAC cable runs common in exchange co-location facilities.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: BCM84894B0IFSBG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | BCM84891B0IFSBG | BCM84848B0IFSBG | BCM84894A0IFSBG |
|---|---|---|---|---|
| Brand | Broadcom | Broadcom | Broadcom | Broadcom |
| Package | FBGA | FBGA - same family | FBGA - same family | FBGA - same |
| Max Per-Port Rate | 100G | 100G | 40G (older generation) | 100G |
| Multi-Rate (10G/25G/100G) | Yes | Yes | Limited (no 100G) | Yes |
| Backplane Interface | KR / CR | KR / CR | KR / CR | KR / CR |
| IEEE 1588v2 Timestamping | Yes | Yes | Limited | Yes |
| Silicon Revision | B0 | B0 | B0 | A0 (older) |
主な差別化要因
- Quad-port density with per-port 100G capability （vs BCM84891B0IFSBG)
- Higher per-port rate ceiling vs 40G legacy family （vs BCM84848B0IFSBG)
- Latest silicon revision with errata fixes （vs BCM84894A0IFSBG)
設計ノート
Estimated: at full 100G x4 configuration the BCM84894B0IFSBG dissipates several watts and requires a thermal-via array under the FBGA plus chassis airflow. Use the Broadcom datasheet theta-JA with your PCB copper stack-up to compute junction temperature rise. For high-density 1U switch designs, design the chassis airflow to provide at least 1-2 m/s across the device thermal pad.
Route 25G/100G KR/CR lanes as 100-ohm differential stripline with controlled impedance and skew under 1 ps. Use low-loss PCB material (Megtron 6 or equivalent) for backplane traces longer than 8 inches. Place AC-coupling capacitors within 200 mil of the BCM84894B0IFSBG transmitter balls and ensure the reference clock has a clean, low-jitter source such as a dedicated TCXO or SI5341.
Validate the backplane or DAC cable channel loss budget against the IEEE 802.3bj/bm insertion-loss template before committing to layout. The BCM84894B0IFSBG adaptive CTLE/DFE/FFE compensates up to ~30 dB loss at Nyquist but cannot rescue a poorly designed channel. Run a pre-layout channel simulation using the IBIS-AMI model from Broadcom to confirm eye-margin margins > 50 mV at the receiver.
Do not omit the per-port MDIO or I2C management interface; firmware is required for auto-negotiation, KR training, and 1588 timestamping configuration. Ensure the BCM84894B0IFSBG reset sequence follows the datasheet power-rail timing - out-of-order ramp-up can leave the PHY in an undefined state requiring a power cycle. Always use the latest Broadcom reference firmware release notes for known errata on the B0 silicon revision.
コンプライアンス情報
RoHS compliance per Broadcom BCM84894 product page environmental section. AEC-Q100 is not applicable (data center / networking IC, not automotive-grade). Confirm halogen-free status and full REACH declaration with Broadcom sales for production documentation.
