CD4018BE - CMOS Divide-by-N Counter | Texas Instruments
部品番号: CD4018BE ✓ 生産中CD4018BE 概要
A CMOS divide-by-N counter is a sequential digital logic device that advances its internal count on each active clock transition. The CD4018 family supports configurable counting behavior through its clock, clock-reset, set, and master-reset controls. It is useful when a system needs programmable frequency division, event-counting, timing generation, or cyclic sequencing without implementing the counter from individual gates. Its fully static operation and 100% testing for quiescent current at 20 V support predictable behavior across the documented supply range.
The principal features of the CD4018BE include medium-speed operation, standardized and symmetrical output characteristics, and parametric operation at 5 V, 10 V, and 15 V. Positive-edge triggering defines when the counter state changes, while the SET and MR inputs provide the controls needed for preset and master-reset functions. Because it uses CMOS technology, the device belongs to the low-power logic family and can support both conventional low-frequency control and higher-frequency timing tasks.
The 16-PDIP package provides through-hole access to all device terminals and is suitable for prototyping, educational equipment, laboratory instruments, industrial controllers, and legacy industrial-control systems. Designers should account for the relatively large footprint compared with surface-mount logic packages and should confirm signal timing at the actual VDD value, because maximum operating frequency is power-supply dependent. The 3 V to 18 V operating range also allows the counter to be used in legacy CMOS systems without an immediate conversion to modern low-voltage logic levels.
Typical applications include divide-by-N frequency dividers, programmable timers, digital frequency measurement stages, sequential timing generators, phase and frequency-related signal processing, and general-purpose counter blocks in control equipment. In a frequency-divider arrangement, the counter can reduce an incoming pulse rate while the SET and MR controls establish operating states. In a microcontroller-assisted instrument, it can provide additional counting or timing resolution beyond the controller's native resources.
The primary design consideration is validating the clock edge, reset timing, output behavior, and maximum transition rate at the actual supply voltage. Inputs and outputs must remain within the device's specified voltage and current limits, and unused inputs should be connected to defined logic levels rather than left floating. The DIP package also requires adequate clearance around adjacent board components and attention to lead strain during insertion or rework.
This page combines the manufacturer's CD4018B technical information, documented supply and speed characteristics, verified cross-reference findings, pin-compatible replacement analysis, comparison parameters, and practical implementation guidance to support faster component selection and board-level planning.
ドロップイン代替品: CD4018BE — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: CD4018BE （同一形状・フットプリント） — 相違点: Package.
CD4018BF
✅ ドロップイン価格はお問い合わせください
データシートを見る →MC14018BCPG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
CD4018BE 最大定格＆電気的特性
| Counter Type | CMOS presettable divide-by-N counter |
| Logic Family | CMOS |
| Number of Counter Elements | 1 element |
| Counter Width | 5 bit |
| Counting Edge | Positive edge |
| Supply Voltage Range | 3 V to 18 V |
| Maximum Operating Frequency | 8.5 MHz |
| Typical Medium-Speed Operation | 10 MHz at VDD minus VSS of 10 V |
| Maximum Input Current | 1 uA at 18 V |
| Operation Mode | Fully static |
| Quiescent Current Test Condition | 100% tested at 20 V |
| Parametric Voltage Ratings | 5 V, 10 V, and 15 V |
| Output Characteristics | Standardized, symmetrical output characteristics |
| パッケージ | 16-PDIP |
| Package Pin Count | 16 pins |
| 実装タイプ | Through-hole |
| Manufacturer Product Lifecycle | Active |
CD4018BE 16 pins ピン配置ガイド
CD4018BE (16 pins パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: CD4018BE.
詳細は データシート をご参照ください。
主な用途
CD4018BE の用途: 6 件s: Programmable Frequency Divider, Digital Frequency Counter Stage, Industrial Timing Generator, Laboratory Pulse Counter, Legacy Control System Counter, Event Counter and Sequencer.
Programmable Frequency Divider
The CD4018BE fits programmable frequency-divider stages because it is a positive-edge CMOS divide-by-N counter operating from 3 V to 18 V. According to the TI CD4018B data sheet, the device is characterized up to 8.5 MHz and supports a typical 10 MHz medium-speed condition at a 10 V supply difference. Place it between the incoming clock and the divided clock output, then use its set and master-reset controls to establish the required counting state. Designers should verify the actual division ratio, reset timing, and output transition rate at the lowest supply voltage used by the circuit.
おすすめ
Digital Frequency Counter Stage
The CD4018BE can serve as the counting stage in a digital frequency-measurement instrument, counting input pulses on its positive clock edge. Its documented 3 V to 18 V supply range supports legacy CMOS test equipment, while the 8.5 MHz characterized rate provides useful bandwidth for moderate-frequency measurement channels. The 5-bit counter element and programmable divide behavior can be combined with external logic to extend the measurement range. Keep the input pulse amplitude and edge shape within the electrical limits shown in the manufacturer data sheet, and account for propagation delay when calibrating the measurement path.
おすすめ
Industrial Timing Generator
The CD4018BE is suitable for industrial timing and sequencing blocks that need selectable counting intervals and deterministic reset behavior. According to the TI CD4018B data sheet, the counter is fully static and supports set and master-reset functions, allowing it to produce repeatable timing waveforms in combination with external gates. Its 3 V to 18 V operating range accommodates legacy industrial-control voltage levels, while the through-hole 16-PDIP package simplifies inspection and replacement. Confirm reset release timing, clock duty cycle, and worst-case timing margin under the intended temperature and supply tolerance.
おすすめ
Laboratory Pulse Counter
The CD4018BE can count pulses in laboratory and educational timing systems while preserving compatibility with classic CMOS logic. Its positive-edge counting behavior, 5-bit counter element, and documented 8.5 MHz operating point support pulse counting beyond slow electromechanical inputs. According to the TI CD4018B data sheet, the device operates from 3 V to 18 V and is fully static, making it appropriate for reproducible bench circuits. Use a defined logic state for every unused control input and include instrumentation or logic analysis when verifying unusual reset and clock combinations.
おすすめ
Legacy Control System Counter
The CD4018BE is appropriate for legacy control systems that retain through-hole CMOS logic and require an adjustable divide-by-N stage. Its 16-PDIP construction matches the package style used in many older industrial and instrumentation designs, while the 3 V to 18 V supply range supports compatibility with established circuit voltages. According to the TI CD4018B data sheet, the counter provides standardized, symmetrical outputs and positive-edge operation. Before incorporating it into a new board, compare timing at the actual VDD and review whether modernization toward smaller surface-mount packages would offer a better long-term maintenance path.
おすすめ
Event Counter and Sequencer
The CD4018BE can turn an event stream into a sequence of digital outputs, making it useful for batch counting, step sequencing, and repetitive industrial controls. Its 5-bit counter element and programmable divide behavior allow external decoding logic to derive multiple timing states. According to the TI CD4018B data sheet, the device counts on the positive edge and offers set and master-reset inputs for initialization and emergency clearing. Validate every asynchronous control sequence and confirm that the output timing remains acceptable at the minimum operating voltage and temperature expected in the equipment.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: CD4018BE — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | CD4018BF | MC14018BCPG |
|---|---|---|---|
| Package | 16-PDIP | 16-pin DIP, ceramic-DIP construction | 16-pin DIP |
| Brand | Texas Instruments | Texas Instruments | onsemi |
| Counter Function | Presettable divide-by-N counter | Presettable divide-by-N counter | Divide-by-N counter |
| Logic Technology | CMOS | CMOS | CMOS |
主な差別化要因
- Exact TI ordering source for the original 16-PDIP design （vs MC14018BCPG)
- Documented 3 V to 18 V operating range （vs CD4018BF)
- Fully static operation with characterized medium speed （vs MC14018BCPG)
設計ノート
Check clock-edge quality and propagation delay at the actual VDD rather than relying only on the 8.5 MHz characterized frequency. The TI CD4018B data sheet also lists a typical 10 MHz medium-speed condition at a 10 V supply difference, showing why the usable rate varies with voltage. Keep the clock source edge rate adequate for the CMOS inputs, preserve the specified logic levels, and account for setup and reset timing around the SET and MR controls.
Operate the counter from a supply inside its documented 3 V to 18 V range and include decoupling close to the VDD and VSS pins. Because the maximum input-current specification is stated as 1 uA at 18 V, do not interpret that figure as the total supply-current budget or as a substitute for checking the complete circuit. Validate the supply range during power-up, reset, and load transitions, and avoid exceeding the absolute limits stated in the manufacturer documentation.
The 16-PDIP format requires through-hole footprint and adequate clearance for insertion, soldering, and component replacement. Follow the package drawing rather than deriving dimensions from a generic DIP drawing. Route the clock away from adjacent switching nodes, provide a solid ground reference, and place any local bypass capacitor close to the supply terminals. Confirm orientation from the package marking and the manufacturer pin-description table.
Do not substitute CD4026BE or CD4022BE solely because they are related CMOS counters. CD4018BE provides a configurable divide-by-N function, while the other devices have different count organizations and output arrangements. Likewise, confirm that CD4018BF and MC14018BCPG meet the original mechanical, timing, temperature, and sourcing requirements. Review the complete state diagram to prevent incorrect set, master-reset, or clock/reset sequencing.
コンプライアンス情報
The CD4018B is a conventional industrial CMOS logic IC rather than an automotive-qualified device. Current RoHS, REACH, lead-free, halogen-free, and conflict-minerals declarations were not identified in the product listing and should be obtained from the manufacturer for the exact ordering code.