CD4045BF - 21-Stage CMOS Counter | Texas Instruments
部品番号: CD4045BF ✗ 生産終了CD4045BF 概要
A counter is a sequential digital circuit that stores and advances a binary count when a clock edge occurs. The CD4045BF belongs to the CMOS logic hierarchy, combining counter, divider, frequency-measurement, and timing functions in one integrated circuit. Its 21-stage architecture allows a clock input to be divided into lower-frequency signals, making it useful when a system needs repeatable counting without a microcontroller or discrete flip-flop chain.
The CD4045BF uses negative-edge clock triggering, so the counter advances on the transition toward the low state of the clock input. A clock-inhibit input provides an external way to prevent counting, while a master-reset path supports initialization of the counter state. Because these functions are implemented in CMOS, the device is particularly appropriate for low-power digital systems, including portable instrumentation and battery-operated control equipment.
The 16-CDIP construction provides a through-hole package for conventional PCB assembly. Its staggered, relatively long leads support hand insertion and leaded through-hole processes where a surface-mount package would be unsuitable. Circuit layout should reserve adequate clearance around the package and route the clock and inhibit signals away from sensitive analog sections to reduce unintended coupling.
Typical uses include divide-by-N clock generation, event and pulse counting, time-interval measurement, periodic digital sequencing, and low-power timing systems. The 21-stage count range allows one input clock to represent a substantially longer interval than the input frequency alone, while the external reset and inhibit controls let a controller coordinate measurement or disable the count during critical periods.
Design the surrounding circuit around the CD4045BF's CMOS supply requirements and verify operating limits against the manufacturer datasheet. Keep the clock waveform clean, use a suitable reset strategy for the target logic state, and do not assume that the inhibit input can substitute for reset. These practices reduce the risk of metastability, unintended counting, or inconsistent startup behavior.
This product page consolidates the exact device identity, package information, technical specifications, source links, practical applications, and verified drop-in alternatives. It also highlights design considerations that help engineers evaluate clocking, reset sequencing, power behavior, and PCB implementation before placing CD4045BF into a new or legacy design.
ドロップイン代替品: CD4045BF — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
CD4045B
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
CD4045BE
✅ ドロップイン ⚠️ 仕様未検証価格はお問い合わせください
データシートを見る →CD4045BF 最大定格＆電気的特性
| Counter Type | Binary counter, 1 element |
| Number of Stages | 21 stages |
| Counter Length | 21 bits |
| Clock Edge Sensitivity | Negative edge |
| Logic Family | CMOS CD4000B series |
| Quiescent Current Test Voltage | 20 V |
| Parametric Rating Voltages | 5 V, 10 V, and 15 V |
| パッケージ | 16-CDIP |
| ピン数 | 16 pins |
| 実装タイプ | Through-hole |
| Power Dissipation | Ultra-low dissipation application |
| JEDEC Qualification | Meets JEDEC Tentative Standard No. 13B for B-series CMOS devices |
CD4045BF ピン構成
| ピン 1 | CLK — Clock input for negative-edge counting |
| ピン 2 | CLK INHIBIT — Clock inhibit input |
| ピン 3 | Q1 — Counter output |
| ピン 4 | Q2 — Counter output |
| ピン 5 | Q3 — Counter output |
| ピン 6 | Q4 — Counter output |
| ピン 7 | Q5 — Counter output |
| ピン 8 | VSS — Ground reference |
| ピン 9 | NC — Not connected |
| ピン 10 | NC — Not connected |
| ピン 11 | NC — Not connected |
| ピン 12 | NC — Not connected |
| ピン 13 | NC — Not connected |
| ピン 14 | NC — Not connected |
| ピン 15 | MR — Master reset input |
| ピン 16 | VDD — Positive supply input |
主な用途
CD4045BF の用途: 6 件s: Frequency Divider, Pulse and Event Counter, Battery-Powered Digital Timer, Time-Interval Measurement, Periodic Digital Sequencer, Low-Power Test Equipment.
Frequency Divider
The CD4045BF is suitable for frequency division because it combines a 21-stage binary counting sequence with negative-edge clock triggering. A stable input clock can be divided into lower-frequency signals when the required ratio corresponds to an accessible counter output. This approach is useful in legacy timing, pulse-rate, and clock-distribution circuits that need low dissipation and can accept the CD4045B's documented operating limits. The PCB should preserve a clean clock path, use defined levels for inhibit and reset, and verify the selected output tap against the manufacturer pin-description table.
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Pulse and Event Counter
The CD4045BF can count incoming pulses in a digital acquisition or control circuit, using its 21-bit counter depth to represent a broad range of accumulated events. Negative-edge clocking allows the counter to advance on a consistent transition of the selected pulse signal, while the clock-inhibit input can stop acquisition without disconnecting the source. This arrangement is appropriate for older industrial counters, test fixtures, and low-power event accumulators. Validate pulse amplitude, width, reset behavior, and maximum clock frequency against the manufacturer data before enabling high-rate counting.
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Battery-Powered Digital Timer
The CD4045BF fits battery-operated timing equipment because the CD4045B family targets digital systems with ultra-low dissipation or battery-source operation. Its 21-stage counter can establish long timing intervals from a periodic clock, allowing a display, indicator, or control output to change less frequently than the oscillator itself. Low-power design still requires attention to every load on the supply rail, because the counter is only one part of the complete power budget. Use the manufacturer's quiescent-current and parametric information to estimate battery life under the intended clock rate and supply voltage.
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Time-Interval Measurement
The CD4045BF can form the counting core of a time-interval measurement system by counting a stable reference clock between two events. Its 21-stage count range provides substantial measurement resolution without requiring a separate counter IC for each additional bit. The clock-inhibit and reset inputs are central to this use because they define when counting starts and when the measured result is initialized. For dependable results, isolate the reference clock from noisy switching nodes and validate input timing, counter rollover, and synchronization behavior against the manufacturer's operating limits.
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Periodic Digital Sequencer
A CD4045BF can provide the timing reference for a periodic digital sequencer by repeatedly advancing a counter and deriving slower state-change events from its outputs. This approach is useful in legacy sequencing, sampling, relay-timing, and repetitive test systems where a small number of discrete counter states is sufficient. The external inhibit and reset controls allow the sequencer to be started, stopped, or initialized deterministically. Logic connected to the counter outputs must respect fan-out, transition timing, and supply-voltage requirements, and unused inputs should be brought to defined levels.
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Low-Power Test Equipment
The CD4045BF is appropriate for legacy low-power test equipment that counts oscillator pulses, divides a reference frequency, or records a limited number of events. Its 21-stage CMOS counter provides useful timing depth while supporting the low-dissipation operating concept associated with the CD4045B family. The 16-CDIP package is also convenient for through-hole prototypes and repair boards that were not designed for fine-pitch surface-mount assembly. For production use, compare modern counter ICs when higher speed, smaller size, broader supply range, or automated surface-mount assembly is more important than retaining the legacy footprint.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: CD4045BF — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | CD4045B | CD4045BE |
|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 16-CDIP | 16-CDIP | 16-CDIP |
| Counter Type | Binary counter, 1 element | Binary counter, 1 element | Binary counter, 1 element |
| Number of Stages | 21 stages | 21 stages | 21 stages |
| Counter Length | 21 bits | 21 bits | 21 bits |
| Clock Edge | Negative edge | Negative edge | Negative edge |
| Logic Family | CMOS CD4000B series | CMOS CD4000B series | CMOS CD4000B series |
| Quiescent Current Test Voltage | 20 V | 20 V | 20 V |
| Parametric Rating Voltages | 5 V, 10 V, and 15 V | 5 V, 10 V, and 15 V | 5 V, 10 V, and 15 V |
主な差別化要因
- Provides a 21-stage counting sequence in one counter element （vs CD4045B)
- Preserves the 16-CDIP through-hole implementation （vs CD4045BE)
- Targets low-dissipation digital equipment （vs CD4045B)
設計ノート
Route the CD4045BF clock as a short, continuous trace away from switching nodes and analog inputs. Because the device advances on a negative clock edge, slow or ringing transitions can create inconsistent counting behavior. Provide a clean ground reference, keep the clock source close to the package, and test the actual edge shape with the intended clock generator and load conditions.
Do not leave the clock-inhibit or master-reset inputs floating. Define their inactive states explicitly and sequence reset release relative to the clock source. Reset initializes the count, while inhibit prevents a clock edge from advancing the counter; treating them as interchangeable can create a one-count offset or an unwanted sequence during startup.
Use a through-hole footprint compatible with the 16-CDIP outline and preserve pin numbering when the board is inserted. Avoid placing tall or heat-sensitive components against the package body, and provide adequate spacing for soldering and inspection. Confirm the manufacturer mechanical drawing before creating or reusing the footprint rather than relying only on the DIP pin count.
Budget the complete supply current rather than considering only the counter's quiescent current. Dynamic current and the load driven by counter outputs depend on clock activity and output transitions. For battery-powered designs, use the manufacturer's quiescent-current and parametric test information and measure the assembled system at the intended voltage and clock rate.
Check rollover behavior before using the CD4045BF as a free-running interval counter. A 21-stage counter does not eliminate the need to define what happens when the count reaches its terminal value. Add external logic, a reset schedule, or a inhibit signal when the application requires a bounded one-shot interval rather than continuous modulo counting.
コンプライアンス情報
Texas Instruments states that the CD4045B meets JEDEC Tentative Standard No. 13B for B-series CMOS devices. RoHS, REACH, lead-free, halogen-free, and conflict-minerals statuses are not stated in the cited product information and therefore remain unknown.