DSPIC33CK128MC102-I/2N - 100MHz 16-bit DSC 128KB Flash | Microchip
部品番号: DSPIC33CK128MC102-I/2N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $3.42 | $3.42 |
| 10 | $3.08 | $30.80 |
| 100 | $2.74 | $274.00 |
| 500 | $2.45 | $1,225.00 |
| 1,000 | $2.18 | $2,180.00 |
DSPIC33CK128MC102-I/2N 概要
A digital signal controller combines the compute architecture of a microcontroller with the DSP capability of a digital signal processor in a single silicon device. Within the power-management hierarchy of embedded systems, a DSC sits between a general-purpose MCU and a dedicated DSP, providing deterministic interrupt latency, single-cycle MAC instructions, and tightly coupled PWM and ADC peripherals, making it the standard choice for real-time control loops in power conversion and motor drive systems.
Key features of the DSPIC33CK128MC102 include a 100 MHz (50 MIPS-class) dsPIC33CK core with DSP-enhanced instruction set, 128 KB Flash with live self-programming, integrated 12-bit ADC capable of high-speed conversions for current-loop control, high-resolution PWM peripherals suited to switch-mode power supplies, and on-chip op-amps that reduce external component count in current-sense signal chains.
Technically, the dsPIC33CK family uses an enhanced pipeline architecture supporting single-cycle MAC and DSP addressing modes, with deterministic interrupt response that is essential for field-oriented control (FOC) and peak-current-mode power conversion. The integrated analog front-end (fast 12-bit ADC, comparators, op-amps) enables single-chip control of a PFC stage plus a downstream converter in many designs.
Typical applications include brushless DC and PMSM motor control, digital power supplies (LLC, buck, boost, PFC), UPS systems, LED drivers, and general embedded control requiring DSP-level math. The 28-pin UQFN footprint suits compact, cost-sensitive boards where a full 64-pin device is unnecessary.
Design consideration: the I-suffix device is rated from -40C to +125C; for extended (-40C to +150C) operation select the E-suffix variant in the same package. All VDD/VSS pairs must be bypassed per the manufacturer datasheet.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: DSPIC33CK128MC102-I/2N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33CK128MC102-I/2N （同一形状・フットプリント） — 相違点: Core, Operating Temperature, PWM.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33CK128MC102-E/2N
✅ ドロップイン✓ 在庫あり
$1.5 / 個
データシートを見る →DSPIC33CK64MC102-I/2N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33CK256MC102-I/2N
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33CK32MC102-I/2N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$0.64 / 個
データシートを見る →DSPIC33CK128MC102-I/2N 最大定格＆電気的特性
| Core | dsPIC33CK 16-bit DSC core |
| Core Speed | 100 MHz |
| Program Memory Size | 128 KB (128K x 8) Flash |
| RAM Size | 16 KB |
| パッケージ | 28-UQFN (6x6 mm) |
| 動作温度 | -40C to +125C (I grade) |
| ADC Resolution | 12-bit |
| On-chip Op-Amps | Yes |
| PWM | High-resolution PWM (per family datasheet) |
| 実装タイプ | Surface Mount |
| インターフェース | UART, SPI, I2C (per family datasheet) |
| Programming Interface | ICSP (multiple PGECx/PGEDx pairs) |
DSPIC33CK128MC102-I/2N ピン構成
| ピン 1 | MCLR — Master clear reset / programming voltage input |
| ピン 2 | AN0/RA0 — Analog input 0 / Port A bit 0 |
| ピン 3 | AN1/RA1 — Analog input 1 / Port A bit 1 |
| ピン 4 | PGED1/AN2/RB0 — Debug/programming data 1 / Analog 2 / Port B bit 0 |
| ピン 5 | PGEC1/AN3/RB1 — Debug/programming clock 1 / Analog 3 / Port B bit 1 |
| ピン 6 | PGED2/AN4/RB2 — Debug/programming data 2 / Analog 4 / Port B bit 2 |
| ピン 7 | PGEC2/AN5/RB3 — Debug/programming clock 2 / Analog 5 / Port B bit 3 |
| ピン 8 | AN6/RB4 — Analog input 6 / Port B bit 4 |
| ピン 9 | AN7/RB5 — Analog input 7 / Port B bit 5 |
| ピン 10 | VSS — Ground reference |
| ピン 11 | VDD — Positive supply |
| ピン 12 | RP15/RB6 — Peripheral Pin Select remappable I/O / Port B bit 6 |
| ピン 13 | RP14/RB7 — Peripheral Pin Select remappable I/O / Port B bit 7 |
| ピン 14 | RP13/RB8 — Peripheral Pin Select remappable I/O / Port B bit 8 |
| ピン 15 | RP12/RB9 — Peripheral Pin Select remappable I/O / Port B bit 9 |
| ピン 16 | RP11/RB10 — Peripheral Pin Select remappable I/O / Port B bit 10 |
| ピン 17 | RP10/RB11 — Peripheral Pin Select remappable I/O / Port B bit 11 |
| ピン 18 | RP27/RB12 — Peripheral Pin Select remappable I/O / Port B bit 12 |
| ピン 19 | RP26/RB13 — Peripheral Pin Select remappable I/O / Port B bit 13 |
| ピン 20 | VSS — Ground reference |
| ピン 21 | RP25/RB14 — Peripheral Pin Select remappable I/O / Port B bit 14 |
| ピン 22 | RP24/RB15 — Peripheral Pin Select remappable I/O / Port B bit 15 |
| ピン 23 | AN9/RA2 — Analog input 9 / Port A bit 2 |
| ピン 24 | AN10/RA3 — Analog input 10 / Port A bit 3 |
| ピン 25 | AN11/RA4 — Analog input 11 / Port A bit 4 |
| ピン 26 | AVSS — Analog ground |
| ピン 27 | AVDD — Analog supply |
| ピン 28 | VSS — Ground reference |
主な用途
DSPIC33CK128MC102-I/2N の用途: 6 件s: BLDC / PMSM Motor Control, Digital Power Supplies (LLC / PFC / Buck), UPS and Inverter Systems, Industrial Automation and Control Panels, Audio Signal Processing, Embedded Sensor and IoT Node Control.
BLDC / PMSM Motor Control
The DSPIC33CK128MC102-I/2N fits sensorless and sensored motor control because its 100 MHz dsPIC33CK core executes single-cycle MAC instructions, sustaining field-oriented control loops at 10-20 kHz update rates with deterministic latency. The fast 12-bit ADC samples phase currents in tight synchronization with the high-resolution PWM peripherals, and the on-chip op-amps amplify shunt-current signals without external amplifiers. Place the DSC between the current-sense shunts and the gate-driver stage of a three-phase inverter; the integrated analog front-end reduces BOM count by removing two external op-amps, while 128 KB Flash holds FOC firmware, commutation tables, and a bootloader with headroom.
おすすめ
Digital Power Supplies (LLC / PFC / Buck)
For switch-mode power conversion, the DSPIC33CK128MC102-I/2N pairs its 100 MHz core with high-resolution PWM that achieves fine duty-cycle and phase resolution, supporting peak-current-mode and voltage-mode control of LLC resonant converters, PFC stages, and synchronous bucks. The 12-bit ADC triggers off the PWM to sample output voltage and inductor current at the optimal point in each switching cycle, minimizing switching-noise corruption. A single chip can close both a PFC loop and a downstream converter loop thanks to DSP throughput. The 28-UQFN (6x6) footprint keeps the controller compact on dense power boards, and the I-grade temperature rating matches sealed PSU environments.
おすすめ
UPS and Inverter Systems
Uninterruptible power supplies require simultaneous AC-mains monitoring, battery management, and inverter waveform generation, which the DSPIC33CK128MC102-I/2N handles with its concurrent ADC sequencing and DSP math. The 100 MHz core computes RMS values, THD correction, and phase-locked-loop grid synchronization in real time, while high-resolution PWM synthesizes a sinusoidal output through the power stage. The 128 KB Flash accommodates transfer logic, battery charging state machines, and communication firmware; 16 KB RAM buffers waveform samples for metering accuracy. The industrial -40C to +125C rating suits telecom outdoor cabinets and industrial backup installations.
おすすめ
Industrial Automation and Control Panels
In factory automation, the DSPIC33CK128MC102-I/2N serves as a compact real-time controller for actuators, pumps, and servo subassemblies. Its UART, SPI, and I2C interfaces link to drives, sensors, and supervisory controllers, while the DSP core runs control algorithms faster than a general MCU of similar cost. The 12-bit ADC digitizes pressure, position, and current feedback, and configurable PWM outputs drive heaters, valves, or small motors directly through drivers. The 28-UQFN (6x6) package suits dense I/O daughter cards, and ICSP programming through any PGECx/PGEDx pair enables in-field firmware updates without board modification.
おすすめ
Audio Signal Processing
The DSP instruction set of the DSPIC33CK128MC102-I/2N supports audio preprocessing tasks such as filtering, limiting, and acoustic echo reduction in cost-sensitive products. At 100 MHz with single-cycle MAC and DSP addressing modes, the controller executes biquad filter banks and level detection across multiple channels while the 12-bit ADC and PWM/DAC-class outputs handle lower-fidelity signal paths typical of intercoms, PA systems, and appliance sound generation. The 128 KB Flash stores filter coefficient sets and multiple audio profiles, and the 16 KB RAM buffers block-based processing. The compact 28-UQFN footprint fits handheld and wall-mounted audio devices.
おすすめ
Embedded Sensor and IoT Node Control
As a host controller for intelligent sensor nodes, the DSPIC33CK128MC102-I/2N combines local DSP filtering with standard connectivity over UART, SPI, and I2C to external radio or wired links. The 12-bit ADC digitizes analog sensor outputs directly, on-chip op-amps condition low-level signals, and the 100 MHz core applies calibration, FFT-based analysis, or thresholding before transmission, offloading gateway processing. Its -40C to +125C industrial range suits outdoor and machinery-mounted nodes. The 28-UQFN (6x6 mm) package occupies minimal board area on compact sensor PCBs, and deep-sleep family power modes extend battery life between transmissions.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33CK128MC102-I/2N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33CK128MC102-E/2N | DSPIC33CK64MC102-I/2N | DSPIC33CK256MC102-I/2N | DSPIC33CK32MC102-I/2N |
|---|---|---|---|---|---|
| Package | 28-UQFN (6x6 mm) | 28-UQFN (6x6 mm) - same | 28-UQFN (6x6 mm) - same | 28-UQFN (6x6 mm) - same | 28-UQFN (6x6 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Speed | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Flash Memory | 128 KB | 128 KB | 64 KB | 256 KB | 32 KB |
| Operating Temperature | -40C to +125C (I) | -40C to +150C (E) | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) |
| ADC / PWM / Op-Amps | 12-bit ADC, HR PWM, on-chip op-amps | 12-bit ADC, HR PWM, on-chip op-amps | 12-bit ADC, HR PWM, on-chip op-amps | 12-bit ADC, HR PWM, on-chip op-amps | 12-bit ADC, HR PWM, on-chip op-amps |
| Pin Compatibility | dsPIC33CK 28-pin 102-pinout | Pin-to-pin identical | Pin-to-pin identical | Pin-to-pin identical | Pin-to-pin identical |
主な差別化要因
- Extended-temperature option in the same footprint （vs DSPIC33CK128MC102-E/2N)
- Flash headroom for bootloader + OTA （vs DSPIC33CK64MC102-I/2N)
- Cost optimization path upward and downward （vs DSPIC33CK256MC102-I/2N / DSPIC33CK32MC102-I/2N)
設計ノート
Connect all VDD and VSS pins - the northernsoftware.com ICSP guidance for dsPIC33CK128MC102 explicitly states all VSS and VDD pins must be connected for programming and reliable operation. Bypass each VDD pin with a 100 nF ceramic capacitor placed within 2 mm of the pin, plus a 4.7-10 uF bulk capacitor near the device. AVDD should be isolated from digital VDD through an LC or ferrite filter to preserve 12-bit ADC accuracy in switching-power applications.
The 28-UQFN (6x6 mm) has a center exposed pad - solder it to a grounded copper pour for thermal relief and signal-return integrity. Route PGECx/PGEDx programming pairs to a header even in production builds; the device has multiple pairs (PGEC1/PGED1, PGEC2/PGED2), and per northernsoftware.com you must use a matched pair, so label your chosen pair on the silkscreen to avoid debug-tool mismatch.
Do not mix PGEC and PGED pairs when wiring ICSP (e.g., PGEC2 with PGED1 will fail). Also note the temperature-grade suffix matters: the -I/2N part is rated to +125C; if your enclosure analysis shows die temperatures above that under worst-case load, switch to the pin-identical DSPIC33CK128MC102-E/2N extended-grade variant rather than derating the firmware budget.
コンプライアンス情報
Compliance data not captured in verified web data as of 2026-09-22; request certificate of conformance from Microchip or distributor.
