DSPIC33EP128GP502-H/SS - 16-bit DSC 60MHz 128KB Flash | Microchip
部品番号: DSPIC33EP128GP502-H/SS ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $5.1 | $5.10 |
| 10 | $4.62 | $46.20 |
| 100 | $4.05 | $405.00 |
| 500 | $3.68 | $1,840.00 |
| 1,000 | $3.25 | $3,250.00 |
DSPIC33EP128GP502-H/SS 概要
A Digital Signal Controller is a hybrid device that merges the control peripherals of a microcontroller (MCU) with the math acceleration of a digital signal processor (DSP). In the power-management hierarchy, DSCs sit between general-purpose MCUs and dedicated DSPs, offering single-cycle MAC and divide instructions plus deterministic interrupt latency for real-time closed-loop control.
Key features include up to 70 MIPS core performance, 128 KB of self-programming Flash with ECC, 16 KB SRAM, high-speed PWM modules suited to power conversion, and a rich analog suite with ADC and op-amp peripherals. Multiple serial interfaces (UART, SPI, I2C) and remappable peripheral pins (PPS) provide flexible I/O design on the 28-pin footprint.
The dsPIC33E architecture uses a modified Harvard pipeline with 16-bit instructions and DSP engine supporting X and Y data memory, enabling FIR/IIR filters and transforms in control loops. ICSP programming and debugging is supported through any PGECx/PGEDx pin pair via MPLAB X IDE with MPLAB SNAP, ICD 3 or REAL ICE tools.
Typical applications include switch-mode power supplies, digital power factor correction, motor control (BLDC/PMSM/ACIM), industrial automation, and high-fidelity audio processing where DSP math and deterministic control are required on a compact 28-pin board.
Design consideration: choose the correct temperature grade suffix - the -H variant operates over a 0C to +85C range, while -I (-40C to +85C) and -E (-40C to +125C) suit harsher environments - and verify VCAP/VDDCORE capacitor placement for core regulation stability.
This page synthesizes distributor availability, same-footprint drop-in alternatives, pinout data, and practical design notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: DSPIC33EP128GP502-H/SS — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33EP128GP502-H/SS （同一形状・フットプリント） — 相違点: Operating Temperature, Communication Interfaces, Package, Analog Peripherals, Core.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33EP128GP502-I/SS
✅ ドロップイン✓ 在庫あり
$2.9 / 個
データシートを見る →DSPIC33EP128GP502-E/SS
✅ ドロップイン✓ 在庫あり
$2.75 / 個
データシートを見る →DSPIC33EP64GP502-I/SS
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EP256GP502-I/SS
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EP256GP502-E/SS
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EP128GP502-H/SS 最大定格＆電気的特性
| Core Architecture | 16-bit dsPIC33E DSC |
| Maximum CPU Speed | 70 MIPS |
| Operating Frequency (this grade) | 60 MHz |
| Flash Memory | 128 KB |
| SRAM | 16 KB |
| Operating Voltage | 3.0 V to 3.6 V |
| 動作温度 | 0C to +85C (-H grade) |
| パッケージ | 28-pin SSOP (SS) |
| 実装タイプ | Surface Mount |
| ADC Resolution | 10/12-bit |
| PWM | High-Speed PWM |
| Analog Peripherals | Op amps, advanced analog |
| Communication Interfaces | UART, SPI, I2C |
| Programming / Debug | ICSP via MPLAB SNAP / ICD 3 / REAL ICE, MPLAB X IDE |
| Pin Remapping | Peripheral Pin Select (PPS) |
| Core Regulator Capacitor | VCAP/VDDCORE pin |
| RoHS ステータス | Lead free / RoHS Compliant |
DSPIC33EP128GP502-H/SS ピン構成
| ピン 1 | MCLR — Master clear reset / ICSP programming voltage input |
| ピン 2 | AN0/VREF+/RB0 — Analog input 0 / positive ADC reference / port B bit 0 |
| ピン 3 | AN1/VREF-/RB1 — Analog input 1 / negative ADC reference / port B bit 1 |
| ピン 4 | AN2/SS1/RB2 — Analog input 2 / SPI slave select 1 / port B bit 2 |
| ピン 5 | AN3/INDX/RB3 — Analog input 3 / encoder index / port B bit 3 |
| ピン 6 | AN4/QEA/IC7/RB4 — Analog input 4 / encoder A input / input capture 7 / port B bit 4 |
| ピン 7 | VDD — Positive supply (3.0 V to 3.6 V) |
| ピン 8 | VSS — Ground reference |
| ピン 9 | OSC1/CLKI/RA2 — Oscillator crystal input / external clock input / port A bit 2 |
| ピン 10 | OSC2/CLKO/RA3 — Oscillator crystal output / clock output / port A bit 3 |
| ピン 11 | AN5/QEB/IC8/RB5 — Analog input 5 / encoder B input / input capture 8 / port B bit 5 |
| ピン 12 | PGD1/AN6/OC1/RB6 — ICSP data 1 / analog input 6 / output compare 1 / port B bit 6 |
| ピン 13 | PGC1/AN7/OC2/RB7 — ICSP clock 1 / analog input 7 / output compare 2 / port B bit 7 |
| ピン 14 | VCAP/VDDCORE — Internal core regulator capacitor connection |
| ピン 15 | PGD3/AN8/RB8 — ICSP data 3 / analog input 8 / port B bit 8 (PPS remappable) |
| ピン 16 | PGC3/AN9/RB9 — ICSP clock 3 / analog input 9 / port B bit 9 (PPS remappable) |
| ピン 17 | AN10/TDI/RB10 — Analog input 10 / JTAG test data in / port B bit 10 (PPS remappable) |
| ピン 18 | AN11/TCK/RB11 — Analog input 11 / JTAG test clock / port B bit 11 (PPS remappable) |
| ピン 19 | AN12/TMS/RB12 — Analog input 12 / JTAG test mode select / port B bit 12 (PPS remappable) |
| ピン 20 | AN13/TDO/RB13 — Analog input 13 / JTAG test data out / port B bit 13 (PPS remappable) |
| ピン 21 | AN14/RB14 — Analog input 14 / port B bit 14 (PPS remappable) |
| ピン 22 | AN15/RB15 — Analog input 15 / port B bit 15 (PPS remappable) |
| ピン 23 | AVSS — Analog ground reference |
| ピン 24 | AVDD — Analog positive supply |
| ピン 25 | PGD2/RP35 — ICSP data 2 / remappable peripheral pin RP35 |
| ピン 26 | PGC2/RP36 — ICSP clock 2 / remappable peripheral pin RP36 |
| ピン 27 | RP41/RF13 — Remappable peripheral pin RP41 / port F bit 13 |
| ピン 28 | RP39/RF2 — Remappable peripheral pin RP39 (I2C data capable) / port F bit 2 |
主な用途
DSPIC33EP128GP502-H/SS の用途: 6 件s: Digital Switch-Mode Power Supplies, BLDC / PMSM Motor Control, Industrial Automation and Control Panels, Power Factor Correction (PFC) Stages, High-Fidelity Audio Processing, Embedded Sensing and IoT Nodes.
Digital Switch-Mode Power Supplies
The DSPIC33EP128GP502-H/SS fits SMPS control because its high-speed PWM module generates complementary outputs with programmable dead time at switching frequencies of tens to hundreds of kHz, while the 70 MIPS DSP core closes voltage and current loops with single-cycle MAC instructions. In a typical buck or boost converter, the ADC samples the output on PWM-triggered conversions and the control law (PI or 3P3Z filter) executes within the switching period. Unlike fixed-function controllers, firmware permits soft-start profiles, fault logging, and protocol-based telemetry over UART or I2C. The 16 KB SRAM accommodates multiple control states and compensation coefficients, and the on-chip op amps can condition current-shunt signals without external amplifiers, reducing BOM cost on compact power boards.
おすすめ
BLDC / PMSM Motor Control
For sensorless or sensored motor drives, the DSPIC33EP128GP502-H/SS provides the high-speed PWM outputs, dead-time insertion, and DSP throughput needed for field-oriented control (FOC) on a 28-pin board. The 70 MIPS core executes Clarke/Park transforms and PI current loops each PWM cycle; quadrature encoder interface inputs (QEA/QEB on RB4/RB5) accept position feedback from incremental encoders. The 12-bit ADC with simultaneous sampling captures phase currents, and integrated op amps amplify shunt signals. Compared with an MCU + gate-driver ASIC stack, this DSC consolidates control into one 3.3 V device. The 128 KB Flash stores FOC libraries plus communication stacks, and Peripheral Pin Select lets designers route PWM and feedback signals to optimal physical pins for the PCB layout.
おすすめ
Industrial Automation and Control Panels
In factory automation nodes, the DSPIC33EP128GP502-H/SS acts as a compact real-time controller combining sensor acquisition, actuation, and communication. Its UART, SPI, and I2C interfaces support RS-485 transceivers, isolation devices, and HMI bridges, while Peripheral Pin Select routes these peripherals to the pins that best suit the panel layout. The industrial-grade -I and extended -E temperature variants of the same die allow one PCB design to serve commercial (-H), industrial (-I), and harsh (-E) deployments without redesign. The 128 KB Flash hosts protocol stacks and diagnostics, and 16 KB SRAM buffers data logging. Multiple PGEC/PGED pairs simplify in-field firmware updates through ICSP with MPLAB SNAP or production programmers, keeping downtime low on installed equipment.
おすすめ
Power Factor Correction (PFC) Stages
Active PFC requires fast current-loop control synchronized to rectified line voltage, a workload the DSPIC33EP128GP502-H/SS handles well. The high-speed PWM drives the boost switch with dead-time-safe gating, ADC conversions are triggered precisely at midpoint of the PWM ramp to average switching ripple, and the DSP engine computes average-current-mode control laws within the 50-100 kHz switching cycle. On-chip comparators and op amps support cycle-by-cycle overcurrent protection with minimal external parts. Running firmware control instead of a fixed analog controller enables adaptive gain across line/load conditions and compliance reporting over a serial link. Designers should budget CPU headroom for the outer voltage loop and verify the 3.0-3.6 V supply is derived from a clean auxiliary rail for ADC accuracy.
おすすめ
High-Fidelity Audio Processing
The dsPIC33EP GP50 family is documented by Microchip and distributors as well-suited to high-fidelity audio processing: the DSP core performs FIR/IIR filtering, equalization, and dynamic-range control with single-cycle multiply-accumulate, while the 128 KB Flash retains coefficient tables and multiple preset profiles. I2S-class audio paths are realized through SPI-framed serial links to external audio codecs, and the 16 KB SRAM holds delay lines for effects such as reverb or active crossover filtering. Deterministic interrupt latency keeps processing jitter low, which matters for audible artifacts. Compared with a general-purpose MCU, the DSC sustains multiply-heavy workloads at a fraction of the clock, reducing EMI in audio products. The -H grade suits consumer/hi-fi indoor equipment; -I covers professional portable gear.
おすすめ
Embedded Sensing and IoT Nodes
As a sensor-node controller, the DSPIC33EP128GP502-H/SS combines multi-channel analog inputs (AN0-AN15 on RB0-RB15), on-chip op amps for signal conditioning, and serial links for LoRa/Wi-Fi module integration over UART. The 12-bit ADC plus DSP filtering (averaging, notch, or FFT-based feature extraction) enables local analytics before transmission, reducing network traffic. Peripheral Pin Select simplifies routing in dense PCBs, and the CTMU-class advanced analog supports charge-time measurement for capacitive touch or ultra-low-cost sensing. With 128 KB Flash, nodes can carry a bootloader plus application, enabling secure field updates via ICSP or serial bootloader. Designers exploiting sleep modes should verify -H grade temperature assumptions, since commercial-grade parts must not be used in unheated outdoor enclosures.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33EP128GP502-H/SS — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33EP128GP502-I/SS | DSPIC33EP128GP502-E/SS | DSPIC33EP64GP502-I/SS | DSPIC33EP256GP502-I/SS |
|---|---|---|---|---|---|
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 128 KB | 128 KB | 128 KB | 64 KB | 256 KB |
| Operating Temperature | 0C to +85C | -40C to +85C | -40C to +125C | -40C to +85C | -40C to +85C |
| Max Core Speed | 70 MIPS (60 MHz this grade) | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS |
| High-Speed PWM | Yes | Yes | Yes | Yes | Yes |
| Programming Toolchain | MPLAB X + SNAP/ICD3/REAL ICE | MPLAB X + SNAP/ICD3/REAL ICE | MPLAB X + SNAP/ICD3/REAL ICE | MPLAB X + SNAP/ICD3/REAL ICE | MPLAB X + SNAP/ICD3/REAL ICE |
主な差別化要因
- Commercial-grade price advantage （vs DSPIC33EP128GP502-E/SS)
- Maximum code headroom on the same footprint （vs DSPIC33EP64GP502-I/SS)
- Cost-optimized for fixed firmware （vs DSPIC33EP256GP502-I/SS)
設計ノート
Supply the device from a clean 3.0 V to 3.6 V rail; the -H grade is specified for 0C to +85C so derate any self-heating budget accordingly. Place a low-ESR capacitor on the VCAP/VDDCORE pin (pin 14) exactly as specified in the Microchip family datasheet DS70000657J - this stabilizes the internal core regulator and is the most common cause of erratic reset behavior when underspecified. Decouple each VDD pin with 0.1 uF ceramic close to the pin plus bulk 4.7-10 uF per board.
Keep AVDD (pin 24) and AVSS (pin 23) on a quiet analog supply island separated from digital return paths, especially when the ADC samples PWM-synchronized current in motor or power applications. Use any PGECx/PGEDx pair for ICSP but never mix pairs - if PGEC2 (pin 26) carries ICSPCLK, ICSPDAT must be on PGED2 (pin 25), as documented in Microchip programming guides. Provide a 5-pin ICSP header (MCLR, VDD, GND, PGDx, PGCx) for MPLAB SNAP access.
Select the temperature suffix deliberately: the -H/SS is commercial grade (0C to +85C). Substituting -I or -E variants later is footprint-compatible but changes qualification and price. When migrating code across the dsPIC33EP64GP502/128GP502/256GP502 family, verify Flash usage against the smaller densities and confirm configuration-bit settings match the target device. Peripheral Pin Select assignments must be locked before routing PWM outputs, because RP pin mapping differs across package pin counts.
コンプライアンス情報
Distributor data (BesenChips) lists Lead Free / RoHS Compliant. Not an automotive AEC-Q100 part; REACH and halogen-free status not stated in provided data.
