DSPIC33EV128GM002-I/SO - 16-Bit 70MIPS 5V DSC | Microchip
部品番号: DSPIC33EV128GM002-I/SO ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4.98 | $4.98 |
| 10 | $4.52 | $45.20 |
| 100 | $3.95 | $395.00 |
| 500 | $3.58 | $1,790.00 |
| 1,000 | $3.22 | $3,220.00 |
DSPIC33EV128GM002-I/SO 概要
A digital signal controller combines the computational architecture of a digital signal processor (DSP) with the peripheral set and ease of use of a microcontroller (MCU). Within the power-management hierarchy, the dsPIC33EV family sits above general-purpose 8-bit MCUs and targets real-time embedded control loops where fast math execution - multiply-accumulate, division, and DSP-style instructions - must complete within a single control cycle, such as field-oriented motor control and switch-mode power conversion.
Key differentiating features include the 5V-tolerant 70 MIPS dsPIC DSC core, on-chip DSP engine, embedded Flash with ECC for functional-safety-oriented designs, and an analog suite with high-speed PWM, SENT peripheral, and integrated operational amplifiers, reducing external component count in motor-drive front ends. The 28-SOIC package supports wave soldering and simpler two-layer PCB designs compared with fine-pitch QFN alternatives.
Architecturally, the device pairs a 16-bit modified Harvard pipeline with dedicated DSP addressing modes and dual operands, enabling deterministic interrupt latency. According to Microchip's dsPIC33EVXXXGM00X/10X Family Data Sheet (DS70005144H), the family is positioned for harsh environments such as appliances, industrial drives, and automotive subsystems.
Typical applications include BLDC/PMSM motor control with sensorless field-oriented control, safety-critical appliance control boards, CAN-networked automotive auxiliary modules, and digital power supplies. The integrated CAN 2.0 module and SENT interface make it a strong fit for in-vehicle nodes that must tolerate 5V transients and 12V battery environments.
Design consideration: the core requires approximately 3.3V derived from an internal regulator while I/O operates at 5V - follow the datasheet decoupling guidance (VDDCAP capacitor on the regulator output) and avoid driving any pin above VDD + 0.3V.
This page adds value beyond the datasheet by consolidating drop-in family alternatives, application pairings, design notes, and distributor pricing context in a single citable reference. Pricing shown is as of 2026-09-26.
ドロップイン代替品: DSPIC33EV128GM002-I/SO — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33EV128GM002-I/SO （同一形状・フットプリント） — 相違点: Core, Package, Program Memory, Operating Temperature, RAM.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33EV256GM002-I/SO
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EV64GM002-I/SO
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EV128GM102-I/SO
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EV64GM102-I/SO
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.55 / 個
データシートを見る →DSPIC33EV256GM102-I/SO
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33EV128GM002-I/SO 最大定格＆電気的特性
| Core | dsPIC33EV 16-bit DSC |
| Max CPU Speed | 70 MIPS |
| Program Memory | 128KB (43K x 24) Flash with ECC |
| RAM | 8 KB |
| Supply Voltage (VDD) | 4.5 V to 5.5 V |
| 動作温度 | -40C to +85C (I grade) |
| パッケージ | 28-SOIC (SO) |
| 実装タイプ | Surface Mount |
| CAN Module | CAN 2.0B |
| PWM | High-speed PWM with complementary outputs |
| SENT Peripheral | Yes |
| On-chip Op Amps | Yes (integrated operational amplifiers) |
| RoHS ステータス | Compliant |
| Programming Interface | ICSP (2-wire PGECx/PGEDx) |
DSPIC33EV128GM002-I/SO ピン構成
| ピン 1 | MCLR — Master clear reset (active low) / programming voltage input |
| ピン 2 | AN0 — Analog input 0 / VREF+ / digital I/O |
| ピン 3 | AN1 — Analog input 1 / digital I/O |
| ピン 4 | AN2 — Analog input 2 / digital I/O |
| ピン 5 | AN3 — Analog input 3 / op amp input / digital I/O |
| ピン 6 | AN4 — Analog input 4 / digital I/O |
| ピン 7 | RPn — Peripheral-pin-select digital I/O |
| ピン 8 | VSS — Ground reference |
| ピン 9 | OSC1 — Oscillator crystal input / external clock input |
| ピン 10 | OSC2 — Oscillator crystal output / clock output |
| ピン 11 | RPn — Peripheral-pin-select digital I/O |
| ピン 12 | RPn — Peripheral-pin-select digital I/O |
| ピン 13 | PGED2 — Programming data pin 2 / digital I/O |
| ピン 14 | PGEC2 — Programming clock pin 2 / digital I/O |
| ピン 15 | RPn — Peripheral-pin-select digital I/O |
| ピン 16 | RPn — Peripheral-pin-select digital I/O |
| ピン 17 | RPn — Peripheral-pin-select digital I/O |
| ピン 18 | RPn — Peripheral-pin-select digital I/O |
| ピン 19 | VSS — Ground reference |
| ピン 20 | VDD — 5V supply (4.5 V to 5.5 V) |
| ピン 21 | RPn — Peripheral-pin-select digital I/O |
| ピン 22 | RPn — Peripheral-pin-select digital I/O |
| ピン 23 | RPn — Peripheral-pin-select digital I/O |
| ピン 24 | RPn — Peripheral-pin-select digital I/O |
| ピン 25 | RPn — Peripheral-pin-select digital I/O |
| ピン 26 | PGED1 — Programming data pin 1 / digital I/O |
| ピン 27 | AVSS — Analog ground reference |
| ピン 28 | AVDD — Analog supply / VDDCAP regulator output per datasheet |
主な用途
DSPIC33EV128GM002-I/SO の用途: 6 件s: BLDC/PMSM Motor Control, Automotive Body and Auxiliary Nodes, Appliance Control Boards, Digital Power Supplies and Converters, Industrial Sensing and CAN Gateways, Safety-Oriented Embedded Control.
BLDC/PMSM Motor Control
The DSPIC33EV128GM002-I/SO fits sensorless field-oriented control (FOC) of BLDC and PMSM motors because its 70 MIPS DSP core executes multiply-accumulate and division-heavy current-loop algorithms within single 10-20 kHz PWM cycles. The integrated operational amplifiers condition shunt-resistor phase currents without external op-amp ICs, and the high-speed PWM module generates complementary dead-time-controlled gate signals. Placed between a gate-driver front end and a CAN bus, the DSC closes the FOC loop deterministically while 5V I/O tolerates noisy inverter environments. ECC Flash protects against bit-flips in long-running drive applications; the 128KB program space accommodates FOC plus communication stacks with headroom.
おすすめ
Automotive Body and Auxiliary Nodes
In automotive auxiliary modules - wiper controllers, pump drivers, lighting nodes - the DSPIC33EV128GM002-I/SO provides 5V-tolerant I/O that interfaces directly with 12V-battery-derived sensor signals through simple conditioning, plus a CAN 2.0B controller for in-vehicle networking. The SENT peripheral decodes SAE J2716 sensor streams common in modern vehicles. Operating from a regulated 5V rail with -40C to +85C capability, the DSC survives under-hood-adjacent environments. The ECC Flash mitigates soft-error risk in safety-relevant node firmware. Designers targeting new CAN FD networks should select the pin-compatible GM102 variant instead, keeping the PCB layout unchanged.
おすすめ
Appliance Control Boards
White-goods and appliance controllers benefit from the DSPIC33EV128GM002-I/SO's combination of 5V robustness, integrated analog, and 70 MIPS real-time performance for compressor and fan motor control. The 28-SOIC package is wave-solderable, supporting cost-sensitive high-volume appliance PCB assembly without fine-pitch processes. The 128KB ECC Flash holds the motor-control firmware, user-interface state machines, and fault-logging code in one device, while integrated op amps reduce the bill of materials for current sensing. The SENT peripheral supports modern appliance sensors. Microchip explicitly positions the dsPIC33EV family for appliances operating in harsh electrical environments per the family data sheet.
おすすめ
Digital Power Supplies and Converters
Switch-mode power supplies and DC-DC converters use the DSPIC33EV128GM002-I/SO as the digital compensation controller: the 70 MIPS core executes PID or 3p3z compensator updates at switching frequencies of 100-500 kHz using the high-speed PWM module's phase-shifted and complementary outputs. The ADC samples output voltage and inductor current each cycle for the control loop, while the integrated op amps amplify shunt signals. 5V I/O interfaces directly with feedback dividers referenced to 5V rails. ECC Flash ensures firmware integrity in always-on power infrastructure, and the industrial temperature grade covers telecom and industrial PSU ambient requirements.
おすすめ
Industrial Sensing and CAN Gateways
Factory-floor sensing nodes and protocol gateways leverage the DSPIC33EV128GM002-I/SO's CAN 2.0B controller and rich peripheral-pin-select routing, which lets UART, SPI, and I2C functions map to nearly any available RPx pin - simplifying PCB routing in dense industrial panels. The 70 MIPS DSP engine performs FFT-based vibration analysis or running-RMS current monitoring locally before transmitting condensed diagnostics over CAN. With -40C to +85C operation and 5V noise immunity, the DSC tolerates the electrical harshness of motor cabinets. The 128KB Flash supports field-updatable firmware with a bootloader plus dual-bank application image, improving serviceability of deployed industrial nodes.
おすすめ
Safety-Oriented Embedded Control
Functional-safety-oriented designs - the DigiKey listing identifies this part within Microchip's Functional Safety (FuSa) program - use the DSPIC33EV128GM002-I/SO's ECC Flash for single-bit error correction and Microchip's safety documentation packages for standards compliance workflows. In applications such as e-bike controllers, lift accessories, and industrial interlocks, the deterministic 70 MIPS core executes watchdog-supervised control loops while CRC-checked Flash images guard against corruption. The 5V I/O domain simplifies interface to discrete safety switches without level shifting. Designers should pair the hardware features with Microchip's safety manual and validation collateral and complete system-level analysis per their target standard.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33EV128GM002-I/SO — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33EV256GM002-I/SO | DSPIC33EV64GM002-I/SO | DSPIC33EV128GM102-I/SO | DSPIC33EV64GM102-I/SO | DSPIC33EV256GM102-I/SO |
|---|---|---|---|---|---|---|
| Package | 28-SOIC | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Program Flash | 128KB (43K x 24) ECC | 256KB (86K x 24) ECC | 64KB (21K x 24) ECC | 128KB (43K x 24) ECC | 64KB (21K x 24) ECC | 256KB (86K x 24) ECC |
| CPU Speed | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS |
| CAN Interface | CAN 2.0B | CAN 2.0B | CAN 2.0B | CAN FD | CAN FD | CAN FD |
| Operating Temperature | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) | -40C to +85C (I) |
| Typical Role | Motor control with classical CAN | Headroom for larger firmware on CAN 2.0 networks | Cost-reduced CAN 2.0 node | CAN FD networked motor control | Cost-reduced CAN FD node | CAN FD flagship with max memory |
主な差別化要因
- 5V-tolerant I/O with integrated op amps （vs DSPIC33EP64MC202-I/MM)
- ECC program Flash for functional-safety designs （vs DSPIC33EV64GM002-I/SO)
- Classical CAN 2.0B for legacy vehicle networks （vs DSPIC33EV128GM102-I/SO)
設計ノート
Decouple VDD with a 0.1uF ceramic capacitor placed within 5 mm of each VDD pin, plus a 4.7-10uF bulk capacitor near the device. The internal core regulator output (VDDCAP pin per datasheet) requires exactly the datasheet-specified low-ESR capacitor and must never be loaded externally or driven - violating this corrupts core supply integrity. Estimated: with 70 MIPS operation, supply current is dominated by core clock, so sizing the 5V rail for the datasheet maximum IDD plus I/O load budget prevents brownout during simultaneous flash writes and CAN transmissions.
Keep AVDD/AVSS as a separate analog island: route analog ground as a quiet spur connected to digital ground at a single point near pin 27/28, and place a 0.1uF plus ferrite filter on AVDD. Use the peripheral-pin-select feature to route CAN RX/TX and PWM outputs away from crystal traces on OSC1/OSC2 (pins 9-10); keep crystal loop area minimal with ground guard traces. For in-circuit programming, expose a 5-pin header on PGEC2/PGED2 (pins 14/13) plus MCLR, VDD, and GND per Microchip ICSP layout guidance.
Do not exceed 5.5V on VDD or drive any I/O above VDD + 0.3V - the family is 5V-tolerant only relative to its own rail, not a 12V battery bus; use dividers or clamping for direct battery-sense signals. Per Microchip device documentation, all PGECx/PGEDx pairs must be used as matched pairs during programming (PGEC2 with PGED2, etc.), and every VDD/VSS pin must be connected or ICSP may fail. Leaving configuration-bit fuse settings (oscillator source, watchdog, PWM pin mode) at defaults is a frequent cause of non-booting first prototypes.
Motor-drive PWM edges are the dominant EMI source in dsPIC33EV designs. Use the PWM module's dead-time and edge-alignment controls to avoid shoot-through, and where the application permits, reduce PWM slew by choosing lower-Fcy PWM prescaler settings rather than software dithering. Route gate-driver outputs on their own layer away from the crystal and analog traces, and place a stitch capacitor between power and logic grounds at the driver return. Verify conducted emissions on the CAN bus with a common-mode choke between the CANTX/CANRX transceiver and bus connector.
コンプライアンス情報
RoHS compliant and lead-free per standard Microchip green packaging for this active catalog part; the -I suffix indicates -40C to +85C industrial temperature grade, not AEC-Q100 automotive qualification - confirm automotive-grade variants with Microchip for qualified applications.
