DSPIC33EV128GM106-I/PT - 70 MIPS 5V 128KB ECC Flash DSC | Microchip
部品番号: DSPIC33EV128GM106-I/PT ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $5.3 | $5.30 |
| 10 | $4.79 | $47.90 |
| 100 | $4.27 | $427.00 |
| 500 | $3.82 | $1,910.00 |
| 1,000 | $3.42 | $3,420.00 |
DSPIC33EV128GM106-I/PT 概要
A digital signal controller (DSC) is a hybrid device that combines the deterministic control architecture of a microcontroller with the deterministic math throughput of a digital signal processor. Within the power and signal-processing taxonomy, the DSC sits above general-purpose microcontrollers and below dedicated DSPs, occupying the niche where closed-loop control loops (motor control, power conversion, sensor fusion) benefit from hardware multiply-accumulate (MAC) and barrel-shifter instructions on a 16-bit datapath. The dsPIC33EV family in particular targets robust 5V operation with ECC Flash for functional-safety use cases.
Key features include execution at up to 70 MIPS from a 5V rail, hardware CAN, 4 DMA channels, 7 timers, and dedicated motor-control PWM peripherals. The 128KB of ECC Flash provides single-bit error correction and dual-bit error detection, which is essential for automotive and industrial functional-safety designs governed by IEC 61508 and ISO 26262. A 16-channel 12-bit ADC, op-amp comparators and a 5 ns comparator complete the analog front end.
The dsPIC33E core implements a Harvard architecture with a 16-bit instruction word and DSP-aware extensions, including a single-cycle MAC and a 40-bit accumulator, allowing fractional DSP arithmetic alongside integer MCU operations. Peripheral Pin Select (PPS) provides extensive I/O remapping flexibility, freeing the designer from rigid pin-function assignments.
Typical applications include automotive sensor and touch-control units, industrial motor drives with CAN networking, appliance controllers in high-electrical-noise mains environments, and functional-safety subsystems where ECC Flash and self-test libraries reduce external watchdog complexity. The 5V-tolerant design minimizes level-shifting when interfacing to legacy 5V sensors.
Design consideration: connect all VDD/VSS pin pairs and use any matched PGECx/PGEDx pair consistently for ICSP programming and debugging, because Microchip's programming guidelines require the clock and data pins to come from the same pair. Decouple each VDD with a 0.1 uF ceramic plus a bulk tantalum placed within 5 mm of the pin.
This page synthesizes distributor pricing context, drop-in family alternatives, and practical design notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: DSPIC33EV128GM106-I/PT — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33EV128GM106-I/PT （同一形状・フットプリント） — 相違点: Package, Core Architecture, Operating Temperature Range, Timers, Maximum CPU Speed.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33EV128GM106-E/PT
✅ ドロップイン✓ 在庫あり
$3.6 / 個
データシートを見る →DSPIC33EV128GM106-H/PT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DSPIC33EV128GM106T-I/PT
✅ ドロップイン✓ 在庫あり
$3.86 / 個
データシートを見る →DSPIC33EV128GM106-I/PT 最大定格＆電気的特性
| Core Architecture | dsPIC33E (16-bit DSC, Harvard) |
| Maximum CPU Speed | 70 MIPS |
| Program Flash | 128 KB (43K x 24), with ECC |
| RAM | 8 KB |
| Operating Voltage | 4.5 V to 5.5 V |
| 動作温度 | -40 C to +125 C (industrial, -I suffix) |
| パッケージ | 64-pin TQFP (10x10 mm, 0.5 mm pitch) |
| ADC | 12-bit, up to 16 channels |
| DMA Channels | 4 |
| Timers | 7 |
| CAN | 1 (hardware CAN module) |
| Comparators | Yes, with 5 ns response |
| Op-Amps | Yes, on-chip |
| PWM Channels | Yes, motor-control PWM peripherals |
| Peripheral Pin Select (PPS) | Yes |
| Functional Safety | FuSa-ready, ECC Flash, Class B safety library |
| ICSP Programming | PGECx/PGEDx pairs |
| RoHS | Compliant |
DSPIC33EV128GM106-I/PT 64-pin tqfp (10x10 mm, 0.5 mm pitch) ピン配置ガイド
DSPIC33EV128GM106-I/PT (64-pin tqfp (10x10 mm, 0.5 mm pitch) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33EV128GM106-I/PT.
詳細は データシート をご参照ください。
主な用途
DSPIC33EV128GM106-I/PT の用途: 3 件s: 組込みシステム, IoTデバイス, 産業制御.
組込みシステム
DSPIC33EV128GM106-I/PTを使用した組込みアプリケーションのコア処理。
IoTデバイス
DSPIC33EV128GM106-I/PTを搭載したスマートコネクテッドデバイス。
産業制御
DSPIC33EV128GM106-I/PTを使用した自動化および制御システム。
この製品に関するFAQはありません。
エンジニアリング参考データ: DSPIC33EV128GM106-I/PT — 比較、設計ガイダンス、コンプライアンス情報。
代替品との比較
| パラメータ | この製品 | DSPIC33EV128GM106-E/PT | DSPIC33EV128GM106-H/PT | DSPIC33EV128GM106T-I/PT |
|---|---|---|---|---|
| Package | 64-TQFP (10x10 mm, 0.5 mm pitch) | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same | 64-TQFP (10x10 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 128 KB ECC (43K x 24) | 128 KB ECC | 128 KB ECC | 128 KB ECC |
| SRAM | 8 KB | 8 KB | 8 KB | 8 KB |
| Core Performance | 16-bit, up to 70 MIPS | 16-bit, up to 70 MIPS | 16-bit, 40 MHz core basis | 16-bit, up to 70 MIPS |
| Temperature Grade | Industrial (-40C to +85C, I suffix) | Extended (to +125C, E suffix) | Industrial -40C range | Industrial (I suffix) |
| DMA Channels / Timers | 4 / 7 | 4 / 7 | 4 / 7 | 4 / 7 |
| Packaging Format | Tray | Tray | Tray | Tape & Reel |
主な差別化要因
- 5V-native operation （vs STM32F3 series)
- Extended-temperature same-die upgrade path （vs DSPIC33EV128GM106-E/PT)
- ECC Flash for noise immunity （vs PIC17C756A-33I/PT (legacy))
設計ノート
Connect ALL VDD and VSS pins of the 64-TQFP package to the 5V rail and ground planes - Microchip programming documentation explicitly requires all supply pins connected for reliable ICSP and operation. Place a 100 nF ceramic decoupling capacitor at each VDD/VSS pair, close to the pins, plus bulk capacitance near the regulator. The 10x10 mm TQFP with 0.5 mm pitch requires standard 0.5 mm pitch land patterns per IPC-7351 conventions; verify solder-mask openings for the fine-pitch corners.
When wiring the ICSP header, use clock and data pins from the SAME PGECx/PGEDx pair - the dsPIC33EV128GM106 has multiple pairs and mixing (e.g., PGEC2 for ICSPCLK with PGED1 for ICSPDAT) prevents programming. Per Northern Software device notes, any pair may be used but must be kept matched. Also verify the supply stays within 4.5V-5.5V under all load transients; brownouts below the minimum can corrupt Flash writes during field firmware updates.
The 5V-native core is an advantage but also a thermal consideration: at 70 MIPS with all peripherals active, current consumption is highest of the family operating points (exact Idd figures: consult the family datasheet DS70005144H electrical characteristics tables). Estimated: at a typical 60-80 mA active current from a 5V rail, the DSC dissipates roughly 0.3-0.4 W, which the 64-TQFP theta_JA can handle on a standard 2-layer board without heatsinking; confirm against the datasheet table for your clock configuration.
The 5V I/O domain gives roughly 50% more noise margin than 3.3V logic, which is the family's key value in motor-drive and automotive cabinets - exploit it by routing long sensor lines at 5V levels rather than adding shielded cables for 3.3V signals. For CAN nodes, keep the transceiver (e.g., MCP2551) close to the CAN pins and stub the bus symmetrically. The hardware barrel shifter and MAC instructions run deterministically, so keep ISR paths free of division-heavy code to preserve real-time jitter budgets.
コンプライアンス情報
Compliance status of the exact ordering code is not stated in the reviewed data; verify on the Microchip product page environmental datasheet. The family is positioned by Microchip for automotive applications, and DigiKey lists Functional Safety (FuSa) supported variants within the dsPIC33EV family.
