DSPIC33FJ06GS102AT-I/SO - 16-bit DSC 40 MIPS 6KB Flash | Microchip
部品番号: DSPIC33FJ06GS102AT-I/SO ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4.62 | $4.62 |
| 10 | $4.16 | $41.60 |
| 100 | $3.7 | $370.00 |
| 500 | $3.33 | $1,665.00 |
| 1,000 | $2.98 | $2,980.00 |
DSPIC33FJ06GS102AT-I/SO 概要
A Digital Signal Controller combines the deterministic interrupt latency and control peripherals of a microcontroller with the multiply-accumulate throughput of a DSP core. In the power-management hierarchy, DSCs sit between general-purpose MCUs and dedicated digital-power ASICs, offering programmable flexibility for loop compensation, sequencing, and telemetry in one chip.
Key features include a 16-bit modified Harvard architecture with DSP engine (17-bit x 17-bit single-cycle MAC), 40 MIPS operation at 3.3V, high-resolution PWM modules suited to peak-current-mode and voltage-mode converter topologies, and a 10-bit ADC with simultaneous multi-channel sampling for fast feedback loops such as current sharing and voltage-mode control. The 6KB self-programming Flash supports field firmware updates, while 256 bytes of RAM accommodate control-loop state variables and PI/PID coefficients.
Architecturally, the dsPIC33F GS core pairs a 16-bit RISC CPU with hardware multiply/divide and dual operand fetch, sustaining single-cycle MAC operations that keep digital control-loop latencies predictable. The GS peripheral set is tailored to digital power: complementary PWM outputs with dead-time insertion, fault inputs for cycle-by-cycle current limiting, and ADC triggers synchronized to the PWM period.
Typical applications include AC-DC and DC-DC converter digital control, power factor correction (PFC) stages, LED drivers, battery chargers, and solar micro-inverter sub-circuits. The 40 MIPS core closes current loops in the tens-of-kilohertz range required by these topologies.
A key design consideration is that the industrial-grade I-temperature variant is specified for -40C to +85C; for -40C to +125C environments select the E-temperature DSPIC33FJ06GS102AT-E/SO, which shares the same die and footprint.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: DSPIC33FJ06GS102AT-I/SO — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ06GS102AT-I/SO （同一形状・フットプリント） — 相違点: Package, Core Architecture, Operating Temperature, Packaging, Program Memory Size.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ06GS102A-I/SO
✅ ドロップイン📋 参考代替品（カタログ未掲載）
DSPIC33FJ06GS102AT-E/SO
✅ ドロップイン✓ 在庫あり
$2.98 / 個
データシートを見る →DSPIC33FJ06GS101AT-I/SO
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.95 / 個
データシートを見る →DSPIC33FJ06GS102AT-E/TL
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.18 / 個
データシートを見る →DSPIC33FJ06GS202T-I/SO
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$3.02 / 個
データシートを見る →DSPIC33FJ16GS502-I/SO
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ06GS102AT-I/SO 最大定格＆電気的特性
| Core Architecture | 16-bit dsPIC33F RISC with DSP engine |
| Maximum CPU Speed | 40 MIPS |
| Program Memory Size | 6 KB (2K x 24) Flash |
| RAM Size | 256 Bytes |
| 電源電圧 | 3.3 V |
| パッケージ | 28-pin SOIC |
| 実装タイプ | Surface Mount |
| Special Features | SMPS (digital power) peripheral set |
| 動作温度範囲 | -40C to +85C (I grade) |
| Product Family | dsPIC33FJ GS (Digital Signal Controllers) |
| Packaging | Tape & Reel (w/t/r) |
| データバス幅 | 16 bit |
| Program Memory Type | Flash |
DSPIC33FJ06GS102AT-I/SO 28-pin soic ピン配置ガイド
DSPIC33FJ06GS102AT-I/SO (28-pin soic パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33FJ06GS102AT-I/SO.
詳細は データシート をご参照ください。
主な用途
DSPIC33FJ06GS102AT-I/SO の用途: 6 件s: Digital AC-DC Power Supply Control, Power Factor Correction (PFC), Digital DC-DC Converters, LED Driver Control, Battery Chargers, Embedded Power Telemetry and Sequencing.
Digital AC-DC Power Supply Control
The DSPIC33FJ06GS102AT-I/SO is purpose-built for digitally controlled AC-DC converters, where its 40 MIPS DSP core closes voltage and current loops with deterministic latency. The GS-series PWM module provides complementary outputs with programmable dead-time insertion, while ADC sampling is triggered synchronized to the PWM period so feedback is captured at consistent points in the switching cycle - eliminating beat-frequency jitter that plagues asynchronous sampling. With 6KB Flash, full voltage-mode or peak-current-mode firmware including soft-start, OVP/OCP protection, and basic telemetry fits on-chip. Placed as the sole controller driving gate drivers, it replaces multiple analog control ICs; the trade-off versus analog control is firmware development effort and attention to loop-compensation code execution time at high switching frequencies.
おすすめ
Power Factor Correction (PFC)
For boost-converter PFC stages, the DSPIC33FJ06GS102AT-I/SO executes the fast inner current loop and slower outer voltage loop required to shape input current to follow the rectified line voltage. Its single-cycle 17-bit x 17-bit MAC and 40 MIPS throughput leave ample margin for PI compensation at 100-200 kHz average-current-mode control. The ADC can multiplex between input current, bus voltage, and AC-zero-cross signals synchronized to the PWM, and fault inputs support cycle-by-cycle current limiting during line transients. The 256-byte RAM is sufficient for filter histories and compensation states. Design consideration: budget CPU cycles carefully at high switching frequency, since sensor filtering and housekeeping code share the same core with the control ISR.
おすすめ
Digital DC-DC Converters
The DSPIC33FJ06GS102AT-I/SO controls buck, boost, half-bridge, and full-bridge DC-DC converters where digital control enables adaptive dead-time, mode transitions (CCM/DCM), and PMBus-style configurability. At 40 MIPS, current loops in the 200-500 kHz range are practical with cycle-by-cycle ADC feedback. The GS PWM offers high-resolution timing for tight duty-cycle granularity, and the Flash self-programming feature allows output-voltage setpoints and protection thresholds to be trimmed in production or updated in the field. Compared with fixed-function PWM controllers, this DSC adds sequencing and fault logging in one 28-SOIC footprint. The key trade-off is power consumption and firmware qualification versus the simplicity of analog control for very high-volume, fixed-specification converters.
おすすめ
LED Driver Control
Dimmable LED drivers benefit from the DSPIC33FJ06GS102AT-I/SO's combination of precise PWM generation and fast ADC feedback for constant-current regulation. The controller implements average-current-mode regulation of the LED string with PWM dimming generated on-chip, achieving dimming ratios that fixed analog drivers cannot reach, while integrated comparators and fault inputs provide open-circuit and short-circuit protection with software-defined responses. Because LED fixtures see elevated ambient temperatures, the -40C to +85C I-grade covers most indoor applications, and the pin-compatible DSPIC33FJ06GS102AT-E/SO (to +125C) serves enclosed fixtures. The 28-SOIC's small footprint fits driver boards where analog multi-chip solutions previously dominated the BOM.
おすすめ
Battery Chargers
Multi-chemistry battery chargers use the DSPIC33FJ06GS102AT-I/SO to run the charging power stage (buck or flyback control loop) and the charge-management state machine simultaneously on one chip. The 40 MIPS core executes constant-current/constant-voltage regulation, termination detection, and temperature-qualified charging via NTC monitoring on an ADC channel, while the GS PWM shapes the power conversion. Flash self-programming lets OEMs store chemistry profiles and cycle-count logs in the same 6KB used by control firmware, and 256 bytes of RAM accommodate charge-state variables. Compared with dedicated charger ICs, this approach adds flexibility for proprietary protocols; the cost is firmware certification effort for safety-critical charging profiles.
おすすめ
Embedded Power Telemetry and Sequencing
Beyond converter control, the DSPIC33FJ06GS102AT-I/SO serves as a supervisory power-management controller performing rail sequencing, voltage/current monitoring, and fault logging across a multi-rail board. Its 40 MIPS core services multiple ADC channels for OV/UV/OC supervision with software-defined response times far faster than comparator-only supervisors, and the UART/SPI interfaces report telemetry to a host or baseboard controller. The 6KB Flash holds sequencing tables that can be re-flashed in the field to accommodate board revisions - a key advantage over hard-coded hot-swap and sequencer ICs. Design consideration: because supervision depends on firmware, watchdog configuration and fail-safe defaults for the PWM outputs must be treated as safety-critical code paths during qualification.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ06GS102AT-I/SO — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ06GS102A-I/SO | DSPIC33FJ06GS102AT-E/SO | DSPIC33FJ06GS101AT-I/SO | DSPIC33FJ06GS202T-I/SO | DSPIC33FJ16GS502-I/SO |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 28-SOIC | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same |
| Core / MIPS | 16-bit dsPIC33F, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS |
| Program Flash | 6 KB (2K x 24) | 6 KB | 6 KB | 6 KB | 6 KB | 16 KB |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Temperature Range | -40C to +85C (I grade) | -40C to +85C | -40C to +125C | -40C to +85C | -40C to +85C | -40C to +85C |
| SMPS Peripheral Set | Yes (GS digital power family) | Yes | Yes | Reduced configuration | Yes, expanded PWM/ADC | Yes, expanded |
主な差別化要因
- SMPS-optimized peripheral set （vs DSPIC33FJ06GS101AT-I/SO)
- Extended temperature option on identical die （vs DSPIC33FJ06GS102AT-E/SO)
- Balanced memory for control-only firmware （vs DSPIC33FJ16GS502-I/SO)
- Tape-and-reel automation （vs DSPIC33FJ06GS102A-I/SO)
設計ノート
Power the DSPIC33FJ06GS102AT-I/SO from a clean 3.3V rail with 0.1 uF ceramic decoupling on every VDD/VSS pin pair, placed within 5 mm of the pins, plus 4.7-10 uF bulk capacitance. Because this is a digital-power controller whose own PWM switching environment generates conducted noise, separate the controller supply from gate-driver supplies with an RC or ferrite filter. Follow Microchip's family datasheet power connection guidelines in document DS-75018B before finalizing the PCB power tree.
Route ADC feedback traces (current shunt, output voltage sense) away from PWM gate-drive nets to prevent switching transients corrupting control-loop samples. Use Kelvin connections at the current shunt and a local analog ground island referenced at a single point. For in-circuit programming, reserve access to the ICSP pins (PGEC/PGED, MCLR) with a 5-pin header - a commonly omitted detail that forces board rework when 6KB firmware must be updated in production.
Confirm the temperature grade before production release: the I-grade part is specified to +85C; designs operating above that (enclosed LED drivers, automotive bays) must use the drop-in DSPIC33FJ06GS102AT-E/SO. Also note the AT suffix denotes tape-and-reel only - it does not change the die. Finally, MCLR requires a pull-up (4.7-10 kohm) and should never be driven below ground; enabling MCLR as a general-purpose input disables low-voltage ICSP programming.
Estimated: when switching MOSFET gates of several nC at 200+ kHz through gate drivers, ground bounce on the controller ground can reach hundreds of millivolts. Keep the PGED/PGEC and oscillator traces short, use a dedicated crystal or the internal FRC oscillator for prototyping, and add series termination (33-100 ohm, estimated values) on long PWM traces to soften gate-drive edges and reduce radiated emissions ahead of EMC testing.
コンプライアンス情報
Compliance statements were not present in the verified web data. Consult the Microchip product page or datasheets.com listing for current RoHS/REACH declarations.
