DSPIC33FJ128GP710A-E/PF - 16-bit DSC 40 MIPS 128KB | Microchip
部品番号: DSPIC33FJ128GP710A-E/PF ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $8.91 | $8.91 |
| 10 | $8.2 | $82.00 |
| 100 | $7.45 | $745.00 |
| 500 | $6.8 | $3,400.00 |
| 1,000 | $6.25 | $6,250.00 |
DSPIC33FJ128GP710A-E/PF 概要
A digital signal controller is a hybrid of a microcontroller (MCU) and a digital signal processor (DSP): it executes general-purpose embedded control code like a 16-bit MCU while adding DSP-class instructions such as multiply-accumulate (MAC), a barrel shifter, and dual operand fetch. Within the power-management and embedded-processing hierarchy, the DSC sits between a standard MCU and a dedicated DSP, making the dsPIC33FJ family a member of the broader 16-bit microcontroller and digital signal processor semiconductor taxonomy.
Key features of the GP710A variant include the 16-bit modified Harvard architecture core running at 40 MIPS from an internal PLL, 128 KB (128K x 8) of self-programmable FLASH, on-chip 12-bit ADC peripherals, multiple UART, SPI, and I2C communication ports, and ICSP/ICD programming with multiple PGECx/PGEDx pin pairs. The A-suffix silicon revision corrects errata found on the original dsPIC33FJ128GP710, making it the preferred choice for new designs.
Technically, the dsPIC33FJ core provides fixed-point DSP capability with dual 40-bit accumulators, hardware division support, and DMA resources, allowing single-cycle MAC operations for filtering, FFT, and control-loop algorithms while retaining deterministic interrupt latency typical of MCUs.
Typical applications include digital power supplies and power-factor-correction converters, motor control inverters, sensor signal conditioning, and general-purpose industrial control where the -40C to +125C extended temperature grade (E suffix) supports harsh environments.
Design consideration: verify that all VDD/VSS pairs are decoupled and that the selected PGEC/PGED pair used for ICSP programming is matched as a pair per the programming specification.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet, with pricing as of 2026-09-26.
ドロップイン代替品: DSPIC33FJ128GP710A-E/PF — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: DSPIC33FJ128GP710A-E/PF （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Core Architecture, RoHS Status, ADC.
クイック比較ツール — 並列比較する代替部品を選択:
DSPIC33FJ256GP710A-E/PF
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$8.45 / 個
データシートを見る →DSPIC33FJ64GP710A-E/PF
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$6.1 / 個
データシートを見る →DSPIC33FJ128GP710-E/PF
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128MC710A-E/PF
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$10.43 / 個
データシートを見る →DSPIC33FJ256GP710-E/PF
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
DSPIC33FJ128GP710A-E/PF 最大定格＆電気的特性
| Core Architecture | 16-bit dsPIC33F (MCU/DSC) |
| Maximum CPU Speed | 40 MIPS |
| Program Memory Size | 128 KB (128K x 8) FLASH |
| パッケージ | 100-TQFP (14x14 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +125C (E grade) |
| Communication Interfaces | UART, SPI, I2C |
| Programming Interface | ICSP/ICD (multiple PGECx/PGEDx pairs) |
| DMA Support | Yes (DMA RAM included) |
| RoHS ステータス | Compliant |
| Lead Free | Yes |
| Product Family | dsPIC33FJXXXGPX06A/X08A/X10A |
DSPIC33FJ128GP710A-E/PF 100-tqfp (14x14 mm) ピン配置ガイド
DSPIC33FJ128GP710A-E/PF (100-tqfp (14x14 mm) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: DSPIC33FJ128GP710A-E/PF.
詳細は データシート をご参照ください。
主な用途
DSPIC33FJ128GP710A-E/PF の用途: 6 件s: Digital Power Supplies and PFC, Motor Control Inverters, Sensor Signal Conditioning and DAQ, Industrial Automation and PLC I/O, Audio and Speech Processing, Portable Instrumentation and Test Equipment.
Digital Power Supplies and PFC
The DSPIC33FJ128GP710A-E/PF fits digital power applications because its 40 MIPS core executes single-cycle DSP multiply-accumulate instructions for current-loop and voltage-loop control at switching frequencies in the tens of kilohertz, while 128 KB FLASH holds compensation firmware, state machines, and communication stacks simultaneously. In a typical topology, the controller samples input/output voltages and inductor current with its on-chip ADC, computes the duty correction in a fast ISR, and drives PWM outputs toward the power stage. Unlike analog-only control, firmware-based control allows adaptive compensation and field updates. The extended -40C to +125C grade tolerates converter ambient conditions near hot components, and DMA RAM offloads sample buffering from the CPU, keeping loop jitter low.
おすすめ
Motor Control Inverters
For BLDC, PMSM, and ACIM drive systems, the DSPIC33FJ128GP710A-E/PF provides the 40 MIPS throughput and hardware MAC needed for field-oriented control (FOC) transformations (Clarke/Park) executed at PWM frequency. Its 100-pin TQFP exposes enough I/O for a three-phase inverter: multiple PWM channels, encoder or resolver inputs, and several UART/SPI ports for gate-driver and host communication. The -40C to +125C E-grade rating is essential inside sealed drive enclosures. Note that Microchip's pin-compatible MC-series variant, the DSPIC33FJ128MC710A, offers a motor-control-optimized peripheral mix on the identical footprint - designers should compare both before freezing the schematic. ADC coordination and DMA RAM help keep current sampling synchronized to PWM, minimizing torque ripple.
おすすめ
Sensor Signal Conditioning and DAQ
The DSPIC33FJ128GP710A-E/PF serves data-acquisition and sensor-front-end designs by combining on-chip ADC sampling with DSP filtering (IIR/FIR) executed at 40 MIPS, so raw sensor signals can be conditioned, decimated, and linearized entirely in firmware. The 100-pin package supplies abundant I/O for multiplexed sensor arrays, and multiple UART/SPI/I2C ports stream processed data to hosts or radios. Applications include industrial transmitters, weighing systems, and vibration monitors where the extended temperature range and RoHS compliance ease certification. Firmware-side DSP avoids an external filter DSP, reducing BOM cost; the trade-off is that 16-bit fixed-point math must be scaled carefully for wide dynamic range. DMA RAM maintains continuous sampling during processing bursts without CPU intervention.
おすすめ
Industrial Automation and PLC I/O
In factory automation, the DSPIC33FJ128GP710A-E/PF acts as an intelligent I/O or motion-axis controller: 40 MIPS performance handles communication protocol stacks alongside control tasks, 128 KB FLASH stores protocol firmware plus application logic, and the rich 100-pin I/O interfaces counters, relays, encoders, and sensors. Multiple UART/SPI/I2C ports support RS-485/Modbus gateways, and the -40C to +125C rating survives control-cabinet temperature extremes. Deterministic interrupt response gives predictable scan times that general-purpose MCUs struggle to match under load. Because the dsPIC33FJ family is broadly second-sourced through distribution (DigiKey, Mouser, LCSC all stock it), maintenance organizations value its long-term availability. ICSP field programming permits firmware updates on installed hardware via the PGEC/PGED pins.
おすすめ
Audio and Speech Processing
The GP-series DSPIC33FJ128GP710A-E/PF suits embedded audio applications such as noise cancellation, speech enhancement, and tone generation: its single-cycle MAC and dual 40-bit accumulators execute FIR/IIR filters and FFTs efficiently at 40 MIPS, while 128 KB FLASH retains coefficient tables and application code. ADC input plus PWM or codec interfacing over SPI forms a complete capture-process-playback path, and the plentiful 100-pin I/O supports buttons, displays, and multiple audio channels. The extended temperature grade enables automotive-adjacent and outdoor communication devices. Fixed-point scaling must be engineered to avoid clipping in wide-dynamic-range audio; the dual accumulators help manage intermediate overflow. Latency is deterministic, an advantage over OS-based processors for real-time echo cancellation.
おすすめ
Portable Instrumentation and Test Equipment
Handheld and bench instruments benefit from the DSPIC33FJ128GP710A-E/PF's balance of DSP math and MCU peripherals: 40 MIPS supports real-time waveform analysis and metering calculations, the ADC captures measurement channels, and UART/USB-bridge-friendly SPI/I2C ports connect displays, memory, and PCs. The 100-pin TQFP provides the I/O count for keypads, rotary encoders, and multi-range front ends in one controller, simplifying the design compared with MCU-plus-DSP two-chip solutions. The -40C to +125C rating supports outdoor test gear, and RoHS/lead-free compliance meets commercial equipment regulations. Battery-powered instruments appreciate the DSC-class performance-per-clock, allowing lower clock operation for the same algorithm throughput, and ICSP enables in-field calibration firmware updates.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: DSPIC33FJ128GP710A-E/PF — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | DSPIC33FJ256GP710A-E/PF | DSPIC33FJ64GP710A-E/PF | DSPIC33FJ128GP710-E/PF | DSPIC33FJ128MC710A-E/PF |
|---|---|---|---|---|---|
| Package | 100-TQFP (14x14 mm) | 100-TQFP (14x14) - same | 100-TQFP (14x14) - same | 100-TQFP (14x14) - same | 100-TQFP (14x14) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Program FLASH | 128 KB | 256 KB | 64 KB | 128 KB | 128 KB |
| Core Type | 16-bit dsPIC33F (GP) | 16-bit dsPIC33F (GP) | 16-bit dsPIC33F (GP) | 16-bit dsPIC33F (GP) | 16-bit dsPIC33F (MC) |
| Silicon Revision | A (errata corrected) | A (errata corrected) | A (errata corrected) | Non-A (errata apply) | A (errata corrected) |
| Operating Temperature | -40C to +125C (E) | -40C to +125C (E) | -40C to +125C (E) | -40C to +125C (E) | -40C to +125C (E) |
主な差別化要因
- Corrected A-version silicon （vs DSPIC33FJ128GP710-E/PF)
- Memory headroom upgrade path on same PCB （vs DSPIC33FJ256GP710A-E/PF)
- GP peripheral mix for general embedded designs （vs DSPIC33FJ128MC710A-E/PF)
設計ノート
Connect every VDD and VSS pair on the 100-TQFP; the programming specification requires all power pins connected during ICSP and normal operation. Place a 100 nF ceramic decoupling capacitor at each VDD/VSS pair, as close to the pins as possible, plus bulk capacitance near the board entry. Keep the VDD plane solid under the chip to minimize ground bounce during 40 MIPS switching activity.
The device provides multiple PGECx/PGEDx pairs for ICSP. You may choose any pair, but clock and data must come from the same pair - mixing PGEC2 with PGED3 prevents programming. Reserve the chosen pair on the PCB with a 5-pin header (MCLR, VDD, GND, PGEC, PGED) and avoid loading these pins with pull-downs or LEDs that interfere with programming voltage levels.
Verify the supply voltage tolerance against the family datasheet electrical characteristics before finalizing the regulator; the dsPIC33FJ core has specific VDD operating ranges that must be respected across the full -40C to +125C temperature span. Budget for inrush into the decoupling network and ensure the regulator can source transient current during DSP MAC bursts and flash write operations, which increase instantaneous core current.
コンプライアンス情報
Listed as 'Lead free / RoHS Compliant' in distributor data (Micro-Semiconductor). REACH, halogen-free, and conflict-minerals declarations not stated in provided data - request Microchip compliance certificate.
