EP20K600CF672I6 - 600K APEX 20KC FPGA, 672-BGA, Industrial | Altera
部品番号: EP20K600CF672I6 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $195 | $19,500.00 |
| 500 | $165 | $82,500.00 |
| 1,000 | $142 | $142,000.00 |
EP20K600CF672I6 概要
An APEX 20KC device is a SRAM-based programmable logic device from Altera's APEX family that integrates logic elements, embedded system blocks (ESBs) for memory, and a network of MultiTrack interconnect resources. APEX 20KC belongs to the broader hierarchy of PLDs (programmable logic devices) -> FPGAs (field-programmable gate arrays) -> programmable logic -> semiconductors, sitting between traditional CPLDs and higher-end FPGAs such as Stratix and Cyclone families. It is designed for data-path intensive designs requiring on-chip memory, register-rich datapaths, and high-speed I/O.
Key features of the EP20K600CF672I6 include 600,000 typical gates, 24,320 logic elements, 311,296 bits of embedded memory, and 4 PLLs. The 'CF672' suffix denotes the 672-pin FineLine BGA package, while 'I6' specifies the industrial temperature range of -40C to +85C. MultiCore architecture combines fine-grained logic elements with embedded array blocks (EABs), enabling simultaneous implementation of register-intensive logic and high-density memory functions on a single die.
Architecturally, the APEX 20KC device uses a 0.18-micron CMOS process with six layers of metal interconnect, supporting I/O voltages from 1.8V to 3.3V (LVCMOS, LVTTL, SSTL, HSTL, PCI, and LVDS standards) via dedicated I/O banks. The on-chip PLLs support clock multiplication, division, phase shifting, and clock switching for complex multi-clock designs. The MultiTrack interconnect minimizes routing congestion while preserving timing predictability for high-fanout nets.
Typical applications for the EP20K600CF672I6 include telecommunications line cards, network switches and routers, high-performance DSP pipelines, ASIC prototyping, and industrial control systems. Its large memory bandwidth suits data packet processing, while its rich logic resources support custom protocol implementations. Designers also use APEX 20KC devices in medical imaging front ends, test and measurement instrumentation, and military/aerospace subsystems requiring industrial-temperature silicon.
Design considerations for the EP20K600CF672I6 include careful power-rail decoupling for the core and I/O supplies, thermal management through PCB copper pours and (where needed) forced-air cooling, and signal-integrity planning for high-speed LVDS/GTL+ interfaces. Configuration via Altera's Quartus II design software (legacy support) is required; modern Quartus Prime provides backward compatibility through legacy device support packages.
This page synthesizes distributor pricing, drop-in Altera APEX 20KC alternatives with the same 672-BGA footprint, and practical design notes drawn from the APEX 20K datasheet - information not consolidated in a single manufacturer document.
ドロップイン代替品: EP20K600CF672I6 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K600CF672I6 （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Speed Grade, Process Technology, Family.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K600CF672C7
✅ ドロップイン✓ 在庫あり
$2267.89 / 個
データシートを見る →EP20K600CF672C8
✅ ドロップイン✓ 在庫あり
$322.4109 / 個
データシートを見る →EP20K600CF672C9
✅ ドロップイン✓ 在庫あり
$171 / 個
データシートを見る →EP20K600EFC672-1X
✅ ドロップイン✓ 在庫あり
$980 / 個
データシートを見る →EP20K600CF672I6 最大定格＆電気的特性
| Family | APEX 20KC |
| Device | EP20K600 |
| Typical Gates | 600,000 |
| Logic Elements | 24,320 |
| Embedded Memory Bits | 311,296 |
| Maximum User I/O Pins | 508 |
| Number of PLLs | 4 |
| パッケージ | 672-BGA FineLine BGA |
| Speed Grade | CF |
| Temperature Grade | Industrial (I) |
| 動作温度 | -40C to +85C |
| Process Technology | 0.18 micron CMOS |
| Configuration Method | SRAM (volatile) |
| 実装タイプ | Surface Mount (BGA) |
EP20K600CF672I6 672-bga fineline bga ピン配置ガイド
EP20K600CF672I6 (672-bga fineline bga パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP20K600CF672I6.
詳細は データシート をご参照ください。
主な用途
EP20K600CF672I6 の用途: 6 件s: Telecommunications Line Cards, Network Switches and Routers, High-Performance DSP Pipelines, ASIC Prototyping, Industrial Control Systems, Test and Measurement Instrumentation.
Telecommunications Line Cards
The EP20K600CF672I6's 600,000-gate logic capacity and 508 user I/O pins make it well-suited to telecom line card designs handling T1/E1 aggregation, framer backhaul, and protocol bridging. Its 311,296 embedded memory bits allow on-chip buffering of ATM cells or Ethernet frames without external SRAM, reducing BOM cost. The 4 PLLs provide independent clock domains for backplane SERDES, framer logic, and TDM buses, while LVTTL/LVCMOS I/O support direct interfacing to legacy telecom ASICs. Industrial temperature operation ensures reliable deployment in central-office or outdoor cabinet environments.
おすすめ
Network Switches and Routers
In Layer 2/3 switching fabrics, the EP20K600CF672I6 implements custom packet parsers, TCAM controllers, and queue managers that benefit from its 24,320 logic elements and large embedded memory. The device's MultiCore architecture lets designers place wide datapaths and parallel lookup engines side by side, achieving multi-Gbps throughput. PCI and LVDS I/O standards interface directly to network processors and PHY chips. Industrial temperature grading supports deployment in uncontrolled-temperature wiring closets and outdoor enclosures.
おすすめ
High-Performance DSP Pipelines
The EP20K600CF672I6 supports DSP pipelines such as FIR filters, FFT cores, and digital downconverters through its embedded system blocks (ESBs), which can be configured as multiplier or RAM structures. With 311 Kbits of on-chip memory and 24,320 logic elements, designers implement multi-tap filters and FFT butterflies without external memory bottlenecks. The 4 PLLs generate the multiple clock phases required by parallel datapaths, while SSTL/HSTL I/O standards interface cleanly to external DDR or ZBT memory. Industrial temperature operation suits ruggedized signal-processing modules.
おすすめ
ASIC Prototyping
Engineers use the EP20K600CF672I6 as an ASIC prototyping vehicle because it offers 600K gates and 508 I/Os - enough capacity to map complex SoC designs before committing to silicon. The SRAM-based configuration supports rapid design iteration, while Quartus II provides synthesis, place-and-route, and timing analysis. PCI, LVDS, and SSTL I/O standards emulate the actual ASIC pad ring, ensuring prototype-to-production timing correlation. Industrial temperature grading also validates thermal behavior before ASIC tape-out.
おすすめ
Industrial Control Systems
The EP20K600CF672I6's industrial temperature range (-40C to +85C) and robust logic capacity suit PLC backplanes, motion controllers, and SCADA interfaces. Its embedded memory holds lookup tables for PID loops and state machines, while the 508 I/Os drive parallel sensor arrays and opto-isolated actuator buses. The MultiCore architecture lets deterministic control logic coexist with statistical process monitoring on a single chip. The 672-BGA package provides the mechanical stability required for industrial vibration and thermal-cycling environments.
おすすめ
Test and Measurement Instrumentation
The EP20K600CF672I6 fits high-channel-count oscilloscope, logic analyzer, and protocol-analyzer front ends where 508 user I/Os directly capture parallel data streams. Its 311 Kbits of embedded memory buffer pre-trigger capture while logic elements implement real-time pattern matching. The 4 PLLs derive multiple sample clocks from a single reference, and LVDS I/O standards interface to high-speed ADCs. Industrial temperature operation supports lab and field-deployed test equipment across wide ambient ranges.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K600CF672I6 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K600CF672C7 | EP20K600CF672C8 | EP20K600CF672C9 | EP20K600EFC672-1X |
|---|---|---|---|---|---|
| Package | 672-BGA FineLine BGA | 672-BGA FineLine BGA - same | 672-BGA FineLine BGA - same | 672-BGA FineLine BGA - same | 672-BGA FineLine BGA - same |
| Brand | Altera | Altera - same | Altera - same | Altera - same | Altera - same |
| Family | APEX 20KC | APEX 20KC - same | APEX 20KC - same | APEX 20KC - same | APEX 20KE (enhanced) |
| Logic Elements | 24,320 | 24,320 - same | 24,320 - same | 24,320 - same | 24,320 - same |
| Embedded Memory (bits) | 311,296 | 311,296 - same | 311,296 - same | 311,296 - same | 311,296 - same |
| Speed Grade | CF | C7 (slower) | C8 (slower) | C9 (slower) | -1X (APEX 20KE timing) |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Industrial temperature grade in same 672-BGA footprint （vs EP20K600CF672C7)
- CF speed grade in same 672-BGA package （vs EP20K600CF672C9)
- APEX 20KC MultiCore architecture （vs EP20K600EFC672-1X (APEX 20KE))
設計ノート
The EP20K600CF672I6 requires separate VCCINT (core) and VCCIO (I/O bank) supplies; typical core voltage is 1.8V with I/O voltages from 1.8V to 3.3V depending on bank configuration. Place 100nF decoupling capacitors adjacent to every VCC pin and bulk tantalum or ceramic capacitors on each supply rail. Power sequencing is recommended: bring up VCCINT before VCCIO to avoid I/O driver latch-up during SRAM configuration.
The 672-ball FineLine BGA package uses a thermally enhanced substrate taller than Altera's regular BGA packages; refer to the Altera Device Package Information Data Sheet for theta-JA and theta-JC values. For continuous operation above 70% logic utilization at industrial temperatures, design at least 4 square inches of inner-plane copper directly under the BGA and consider 200 LFM of forced-air cooling to keep junction temperature within the 125C maximum.
The 672-BGA footprint requires microvia or via-in-pad PCB technology for reliable solder joints; standard through-vias cannot fan out from inner balls. Maintain 50-ohm controlled impedance for LVDS pairs and 60-ohm for SSTL signal traces. Use Altera's reference board layout in the APEX 20K development kit as a starting point for stack-up and via pattern.
Estimated: configuring the EP20K600CF672I6 via an external PROM requires the MSEL pins to be strapped to the correct mode (Fast Passive Parallel, Passive Serial, etc.); incorrect MSEL settings cause configuration failure that mimics a dead device. The 'I6' industrial temperature grade does not guarantee operation above 85C - check junction temperature against the APEX 20K datasheet derating curves for your specific I/O switching activity.
コンプライアンス情報
Compliance status not confirmed in the provided verified web data for this obsolete Altera APEX 20KC part. The part was originally manufactured before strict RoHS enforcement; check with the distributor or Altera (Intel) for historical compliance documentation.
