EP20K60EBC356-2 - APEX 20KE 60K Gate FPGA, 196 I/O, BGA-356 | Intel / Altera
部品番号: EP20K60EBC356-2 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $162 | $1,620.00 |
| 100 | $138.5 | $13,850.00 |
| 500 | $119 | $59,500.00 |
| 1,000 | $98.75 | $98,750.00 |
EP20K60EBC356-2 概要
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit that can be configured by the customer after manufacturing to implement arbitrary digital logic. FPGAs sit within the programmable logic device (PLD) hierarchy - alongside CPLDs - and are positioned above fixed-function ASICs only in terms of flexibility, not raw performance per watt. The APEX-20KE family, in particular, pioneered system-on-a-programmable-chip (SOPC) integration by combining logic, memory, and I/O elements on a single die, enabling glue-logic replacement, custom datapath implementation, and high-throughput interface bridging.
Key differentiating features of the EP20K60EBC356-2 include 60,000 typical gates, 196 user I/O pins, the speed grade -2 designation (a moderate-speed bin suitable for general-purpose designs), and a 1.72 ns pin-to-pin propagation delay. The device supports in-system programmability through the IEEE 1149.1 (JTAG) interface and is supported by the Quartus design toolchain (legacy versions compatible with APEX 20KE include Quartus II and MAX+PLUS II). Operating temperature range is 0 C to 85 C (commercial grade).
From an architectural standpoint, the APEX-20KE MultiCore structure pairs Logic Array Blocks (LABs) with Embedded System Blocks (ESBs) that double as dual-port RAM or ROM, allowing designers to place small FIFOs, register files, or constant tables without consuming general-purpose logic. The 196 I/O pins are distributed across multiple I/O banks with support for multiple I/O standards (LVTTL, LVCMOS, PCI), and each I/O cell contains registers for input, output, and output-enable paths.
Typical applications for the EP20K60EBC356-2 include telecommunications line-card glue logic, industrial control backplanes, custom peripheral bridges for PCI/CompactPCI designs, legacy DSP pre/post-processing, and protocol converter ASICs. The -2 speed grade and 160 MHz internal frequency make the device suitable for control-plane rather than high-speed datapath designs.
When designing with this FPGA, ensure your PCB has adequate decoupling: at least one 0.1 uF ceramic capacitor per VCC pin group plus bulk decoupling on each of the VCCINT and VCCIO rails. A JTAG header with TMS, TCK, TDI, TDO, and TRST (optional) is required for in-system configuration and boundary-scan test. Because this part is mature and nearing end-of-life, designers should plan a long-term component-availability strategy.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
ドロップイン代替品: EP20K60EBC356-2 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP20K60EBC356-2 （同一形状・フットプリント） — 相違点: Family, Operating Temperature, Package, Process Technology, Speed Grade.
クイック比較ツール — 並列比較する代替部品を選択:
EP20K60EBC356-3
✅ ドロップイン✓ 在庫あり
$65.8 / 個
データシートを見る →EP20K60EBC356-1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EP20K100EBC356-2
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EP20K60EBC356-2 最大定格＆電気的特性
| Series | APEX-20KE |
| Family | APEX 20K (MultiCore architecture) |
| Logic Elements / Typical Gates | 60,000 typical gates |
| User I/Os | 196 |
| パッケージ | 356-LBGA (BGA-356, 1.27 mm pitch) |
| Propagation Delay (pin-to-pin) | 1.72 ns |
| Internal Operating Frequency | up to 160 MHz |
| Speed Grade | -2 (moderate speed bin) |
| Process Technology | CMOS |
| 動作温度 | 0 C to +85 C (commercial grade) |
| 実装タイプ | Surface Mount (BGA) |
| Configuration Interface | JTAG (IEEE 1149.1) + passive serial / EPC configuration |
| Design Tool Support | Quartus II, MAX+PLUS II (legacy) |
| ライフサイクル状態 | Not Recommended for New Designs (NRND) - Intel/Altera APEX 20KE family |
EP20K60EBC356-2 356-lbga (bga-356, 1.27 mm pitch) ピン配置ガイド
EP20K60EBC356-2 (356-lbga (bga-356, 1.27 mm pitch) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EP20K60EBC356-2.
詳細は データシート をご参照ください。
主な用途
EP20K60EBC356-2 の用途: 6 件s: Telecommunications Line-Card Glue Logic, Industrial Control Backplane Bridging, Custom Peripheral Bridge for PCI / CompactPCI, Legacy DSP Pre/Post-Processing Pipeline, ASIC Replacement / Low-Volume Custom Logic, Test and Measurement Instrument Backplane.
Telecommunications Line-Card Glue Logic
The EP20K60EBC356-2 is well suited to telecom line-card glue logic where it bridges backplane interfaces to network processors. Its 196 user I/Os provide ample connections for TDM buses, framers, and PHY interfaces, while the embedded system blocks (ESBs) deliver dual-port RAM for cell buffers and lookup tables. The 1.72 ns propagation delay and 160 MHz internal frequency comfortably handle 77.76 MHz STS-12 tributary traffic. At 0.85 W typical dynamic power, the device fits into the thermal envelope of compact line cards. Designers typically pair it with a PowerPC or MIPS control processor over a local bus.
おすすめ
Industrial Control Backplane Bridging
The EP20K60EBC356-2 finds use in industrial PLC and DCS backplanes as a protocol converter between legacy fieldbus interfaces (Profibus, Foundation Fieldbus) and modern Ethernet/IP backbones. Its CMOS MultiCore architecture and embedded memory blocks implement custom state machines and protocol stacks without external SRAM. The 356-LBGA package supports the high pin count required for multi-protocol I/O. Operating temperature 0 C to 85 C matches commercial industrial control environments. Pairing with industrial PHYs and isolated transceivers yields a robust field-deployed bridge.
おすすめ
Custom Peripheral Bridge for PCI / CompactPCI
The EP20K60EBC356-2 implements custom PCI/CompactPCI peripheral bridges where off-the-shelf bridge ICs are unavailable or too expensive. Its I/O banks support PCI 5V and 3.3V signaling directly, and the 196 available I/Os cover the 49-pin PCI connector plus auxiliary control signals. The 60K-gate capacity accommodates full PCI target/master state machines and scatter-gather DMA engines. Embedded memory blocks serve as descriptor FIFOs. The device's commercial temperature range suits indoor CompactPCI chassis environments.
おすすめ
Legacy DSP Pre/Post-Processing Pipeline
The EP20K60EBC356-2 implements pre- and post-processing stages around legacy DSP chips, performing sample-rate conversion, filtering, and protocol framing. Its embedded system blocks (ESBs) hold coefficient ROM tables for FIR filters, while the LUT-based logic fabric executes the multiply-accumulate control sequencing. Although not as DSP-efficient as modern FPGAs, the APEX 20KE suffices for narrowband audio and ultrasonic signal chains at moderate sample rates. The 356-LBGA's thermal performance supports continuous operation in signal-processing enclosures.
おすすめ
ASIC Replacement / Low-Volume Custom Logic
The EP20K60EBC356-2 serves as an ASIC replacement in low-volume or pre-production runs where mask costs for an ASIC are uneconomical. The 60K-gate capacity covers many mid-complexity glue-logic designs, and the JTAG-based configuration enables rapid design iteration. The device is fully supported by MAX+PLUS II and legacy Quartus II toolchains, allowing engineers to maintain existing design IP. For higher volumes, the design can be ported to a structured ASIC or a modern Cyclone FPGA while preserving the original RTL.
おすすめ
Test and Measurement Instrument Backplane
The EP20K60EBC356-2 implements the backplane logic in test and measurement instruments such as logic analyzers, protocol exercisers, and ATE load boards. Its 196 I/Os drive or receive test vectors across many channels simultaneously, and the ESB memory holds stimulus patterns. The 160 MHz internal frequency suits pattern generation up to 200 MHz vector rates. The 356-LBGA package offers the signal integrity required for high-channel-count fixtures. Combined with external comparators, the device forms a flexible ATE stimulus engine.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP20K60EBC356-2 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP20K60EBC356-3 | EP20K60EBC356-1 | EP20K60EQC240-2 | EP20K100EBC356-2 |
|---|---|---|---|---|---|
| Package | 356-LBGA | 356-LBGA (same) | 356-LBGA (same) | 240-PQFP (different) | 356-LBGA (same) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Typical Gates | 60,000 | 60,000 | 60,000 | 60,000 | 100,000 |
| User I/Os | 196 | 196 | 196 | ~148 | 196 |
| Propagation Delay | 1.72 ns | 1.40 ns (faster) | 2.10 ns (slower) | 1.72 ns | 1.72 ns |
| Internal Frequency | 160 MHz | 180 MHz | 133 MHz | 160 MHz | 160 MHz |
| Speed Grade | -2 | -3 (faster) | -1 (slower) | -2 | -2 |
| Operating Temperature | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
主な差別化要因
- Same-die speed grade flexibility on identical footprint （vs EP20K60EBC356-1)
- Higher I/O density on the 356-LBGA package （vs EP20K60EQC240-2)
- 60K-gate density with APEX 20KE MultiCore architecture （vs EP20K100EBC356-2)
設計ノート
The APEX 20KE EP20K60E requires two supply rails: VCCINT for the core logic and VCCIO for the I/O banks (one or more rails depending on bank voltage standards). Place a 0.1 uF ceramic decoupling capacitor within 3 mm of every VCC pin pair, plus 10 uF bulk decoupling on each supply rail near the device. If using multiple I/O voltage standards (e.g., 5 V PCI and 3.3 V LVCMOS), provide separate VCCIO rails for each bank and isolate them with ferrite beads. Estimated: at 100 MHz operation, the EP20K60E typically draws around 0.5-0.85 W from VCCINT depending on toggle rate and utilization.
Use a 6-layer or 8-layer PCB stack-up with dedicated power and ground planes for the 356-LBGA. Route all BGA signals on inner layers with microvias or via-in-pad if budget allows; otherwise dog-bone fan-out is acceptable for signals not exceeding 100 MHz. Maintain 50 ohm single-ended impedance on LVCMOS/LVTTL traces. The 356-LBGA's 1.27 mm pitch is hand-solderable only with hot air or reflow; never attempt hand-soldering with an iron. Place the JTAG header within 50 mm of the device for reliable configuration.
Do not confuse the APEX 20KE family with the original APEX 20K family when ordering; 20KE devices include enhanced ESB features but otherwise share the same JTAG ID chain. When migrating a design from -2 to -3 speed grade, re-run timing analysis because some paths may become marginally slower due to voltage/temperature effects on the -3 device's internal timing. Lastly, APEX 20KE configuration is volatile - the design must be loaded from a configuration EPROM (EPC) or microcontroller on every power-up; do not assume SRAM-based retention.
The 356-LBGA package typically has a junction-to-ambient thermal resistance (theta_JA) in the range of 15-25 C/W on a 4-layer JEDEC test board. Estimated: at 1 W total power dissipation in a still-air 25 C ambient, the junction rises 15-25 C above ambient, which remains within the commercial 85 C limit. For enclosed chassis or >1 W dissipation, add airflow or thermal vias beneath the package thermal pad to the internal ground plane to reduce junction temperature.
コンプライアンス情報
RoHS and lead-free status not confirmed in verified web data. APEX 20KE family is generally not AEC-Q100 qualified - this part targets commercial industrial applications.
