EP610LI-35 - 16-Macrocell Classic EPLD, 35ns, PLCC-28 | Altera
部品番号: EP610LI-35 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14 | $1,400.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.5 | $10,500.00 |
EP610LI-35 概要
A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses EPROM, EEPROM, or Flash cells to store the configuration. CPLDs/EPLDs belong to the broader hierarchy of programmable logic devices (PLDs), which sit between discrete logic ICs and full FPGAs in density and complexity. The Classic family implements a PAL-style AND-OR architecture with macrocells containing flip-flops, making it ideal for glue logic, state machines, and bus interfacing in 5 V systems.
Key features of the EP610LI-35 include PAL-type architecture with 16 macrocells, 160 product terms for wide sum-of-products logic, 4 dedicated inputs plus 2 external clock inputs, and CMOS technology for low power consumption. The device provides in-system programmable logic with high noise immunity typical of CMOS designs, supporting synchronous designs through dedicated clock networks and asynchronous designs through programmable flip-flops.
The EP610 architecture uses a programmable interconnect scheme with each macrocell containing a configurable flip-flop with preset/reset capability. Logic is implemented as sum-of-products terms that feed the 16 macrocell flip-flops, which can be configured as D, T, JK, or SR types. This architecture is well suited to decoder, encoder, and state-machine implementations where deterministic timing is critical.
Typical applications include bus interface glue logic, address decoding, state machines, and peripheral control in legacy 5 V systems. The wide 5 V tolerance makes it suitable for industrial control and replacement of discrete TTL/CMOS logic, particularly in long-lifecycle equipment where modern FPGAs are unsuitable. The windowed ceramic package enables reprogrammability for prototype development and field updates.
When designing with the EP610LI-35, ensure that all unused I/O pins are properly terminated to avoid floating-input issues in CMOS designs. The 35 ns propagation delay must be analyzed against the target system's timing budget, with attention to the worst-case delay paths through multiple logic levels.
ドロップイン代替品: EP610LI-35 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP610LI-35 （同一形状・フットプリント） — 相違点: Family, Package, Mounting Type, Operating Temperature, Macrocells.
クイック比較ツール — 並列比較する代替部品を選択:
EP610LI-30
✅ ドロップイン✓ 在庫あり
$18.5 / 個
データシートを見る →EP610LC-35
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EP610JI-30
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.4 / 個
データシートを見る →EP610DC-35
✅ ドロップイン✓ 在庫あり
$18.4 / 個
データシートを見る →EP910LC-35
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$18.75 / 個
データシートを見る →EP610LI-35 最大定格＆電気的特性
| Family | Classic EPLD |
| Series | EP610 |
| Number of Macrocells | 16 |
| Usable Gates | 300 |
| Number of I/O Pins | 16 |
| Total Inputs | 20 |
| Dedicated Inputs | 4 |
| External Clock Inputs | 2 |
| Product Terms | 160 |
| Maximum Propagation Delay | 35 ns (tpd) |
| Maximum Operating Frequency | 28.6 MHz (fmax) |
| Pipelined Data Rate | Up to 100 MHz |
| 電源電圧 | 5 V |
| Process Technology | CMOS |
| Architecture | PAL-type (AND-OR array) |
| パッケージ | 28-pin PLCC (windowed ceramic, 'LI') |
| Programming Technology | UV-erasable (EPROM) |
| 実装タイプ | Surface Mount |
EP610LI-35 ピン構成
| ピン 1 | I/O0 — Bidirectional I/O pin 0 |
| ピン 2 | I/O1 — Bidirectional I/O pin 1 |
| ピン 3 | I/O2 — Bidirectional I/O pin 2 |
| ピン 4 | I/O3 — Bidirectional I/O pin 3 |
| ピン 5 | I/O4 — Bidirectional I/O pin 4 |
| ピン 6 | I/O5 — Bidirectional I/O pin 5 |
| ピン 7 | I/O6 — Bidirectional I/O pin 6 |
| ピン 8 | I/O7 — Bidirectional I/O pin 7 |
| ピン 9 | I/O8 — Bidirectional I/O pin 8 |
| ピン 10 | I/O9 — Bidirectional I/O pin 9 |
| ピン 11 | I/O10 — Bidirectional I/O pin 10 |
| ピン 12 | I/O11 — Bidirectional I/O pin 11 |
| ピン 13 | I/O12 — Bidirectional I/O pin 12 |
| ピン 14 | I/O13 — Bidirectional I/O pin 13 |
| ピン 15 | I/O14 — Bidirectional I/O pin 14 |
| ピン 16 | I/O15 — Bidirectional I/O pin 15 |
| ピン 17 | IN0 — Dedicated input 0 |
| ピン 18 | IN1 — Dedicated input 1 |
| ピン 19 | IN2 — Dedicated input 2 |
| ピン 20 | IN3 — Dedicated input 3 |
| ピン 21 | CLK0 — External clock input 0 |
| ピン 22 | CLK1 — External clock input 1 |
| ピン 23 | OE — Output enable |
| ピン 24 | VCC — +5 V supply |
| ピン 25 | NC — Not connected (per datasheet) |
| ピン 26 | NC — Not connected (per datasheet) |
| ピン 27 | GND — Ground |
| ピン 28 | PRG — Programming pin |
主な用途
EP610LI-35 の用途: 6 件s: Bus Interface Glue Logic, Address Decoding Circuits, State Machine Implementation, Legacy 5V System Logic Replacement, Peripheral Control Logic, Industrial Control and Automation.
Bus Interface Glue Logic
The EP610LI-35 is well suited as bus interface glue logic in 5 V legacy systems. With 16 macrocells and 35 ns propagation delay, it can decode address buses, generate chip-select signals, and arbitrate bus requests at moderate speeds. Its 16 I/O pins and 4 dedicated inputs allow direct connection to address and control lines, while the 5 V CMOS interface matches TTL/CMOS bus voltages. Compared to discrete 74-series logic, the EP610LI-35 replaces multiple packages with a single programmable device, reducing board area and improving design flexibility.
おすすめ
Address Decoding Circuits
The EP610LI-35's 160 product terms and PAL-type AND-OR architecture make it ideal for address decoding in microprocessor and microcontroller systems. With 16 macrocells and 35 ns tpd, it can decode full 16-bit address spaces with sub-50 ns access times. The 4 dedicated inputs accommodate address and control signals directly, while 16 outputs drive enable lines for memory and I/O peripherals. The UV-erasable windowed package supports multiple design iterations, valuable during prototype development of decoded address maps.
おすすめ
State Machine Implementation
The EP610LI-35 implements finite state machines efficiently with its 16 macrocells, each containing a configurable flip-flop (D, T, JK, or SR). With 35 ns propagation delay and 28.6 MHz fmax, it handles medium-speed control logic in industrial equipment. The 160 product terms provide ample combinational decoding, while dedicated clock inputs support synchronous state transitions. The CMOS low-power design suits battery-backed or power-sensitive industrial applications where state must be retained through power cycles.
おすすめ
Legacy 5V System Logic Replacement
The EP610LI-35 is widely deployed in long-lifecycle industrial equipment where 5 V tolerance is mandatory. With its 5 V supply and CMOS interface, it directly replaces discrete 74LS/74HC logic packages while consolidating multiple functions into one programmable device. The 35 ns speed grade handles peripheral control timing in legacy systems running 8-16 MHz microprocessors. Its windowed ceramic package enables field reprogramming for equipment upgrades, an essential capability for installed industrial systems with decades-long deployment horizons.
おすすめ
Peripheral Control Logic
The EP610LI-35 provides timing and control logic for peripherals such as UARTs, parallel ports, and display drivers in 5 V systems. Its 16 I/O pins and 35 ns tpd enable generation of read/write strobes, interrupt acknowledge signals, and handshake protocols. The PAL-type architecture supports both combinational and registered outputs, allowing flexible peripheral interface implementation. Compared to discrete logic, the EP610LI-35 reduces part count by 5-10x in typical peripheral control designs.
おすすめ
Industrial Control and Automation
The EP610LI-35's CMOS low-power design and 5 V operation make it suitable for industrial control applications including PLCs, motor controllers, and sensor interfaces. With 16 macrocells and 35 ns tpd, it implements deterministic control logic with predictable timing. The windowed ceramic package supports field updates for deployed industrial systems where firmware changes may be required after installation. Compared to modern FPGAs requiring 3.3V or lower supplies, the EP610LI-35 operates directly with 5V industrial sensors and actuators.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP610LI-35 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP610LI-30 | EP610LC-35 | EP610JI-30 | EP610DC-35 | EP910LC-35 |
|---|---|---|---|---|---|---|
| Package | PLCC-28 (windowed ceramic) | PLCC-28 (windowed ceramic) - same | PLCC-28 (plastic) - same | PLCC-28 (windowed ceramic) - same | CDIP-24 - different | PLCC-28 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Speed Grade (tpd) | 35 ns | 30 ns (faster) | 35 ns (same) | 30 ns (faster) | 35 ns (same) | 35 ns (same) |
| Number of Macrocells | 16 | 16 (same) | 16 (same) | 16 (same) | 16 (same) | 24 (higher density) |
| Usable Gates | 300 | 300 (same) | 300 (same) | 300 (same) | 300 (same) | 450 (higher) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) |
| Package Material | Windowed ceramic | Windowed ceramic | Plastic (not windowed) | Windowed ceramic | Ceramic DIP | Plastic |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Same die, lower-cost plastic package alternative available （vs EP610LC-35)
- Drop-in speed grade upgrade available （vs EP610LI-30)
- Higher-density variant available （vs EP910LC-35)
設計ノート
The EP610LI-35 operates from a single 5 V supply with typical CMOS quiescent current in the low milliamp range. Bulk decoupling requires a 10-100 uF electrolytic capacitor near the VCC pin, plus a 0.1 uF ceramic bypass capacitor to suppress switching transients during logic transitions. Multiple VCC/GND pins (where present) should each have their own bypass capacitor to minimize ground bounce during simultaneous output switching.
When using the windowed ceramic PLCC package, ensure adequate clearance above the device for UV erasure - the package window must be accessible for the eraser lamp. For PLCC-28 sockets, use quality machined-pin sockets rather than cheap stamped sockets to ensure reliable contact over decades of operation. Surface-mount variants (if available) require standard SOIC/PLCC land patterns. Keep high-speed signals short and avoid running them parallel to noisy power traces.
Unused I/O pins on the EP610LI-35 must be configured as outputs or terminated to a defined logic level; leaving CMOS inputs floating can cause oscillation and increased supply current. The 35 ns propagation delay is the worst-case specification - typical performance is faster. When upgrading to faster speed grades (EP610LI-30, EP610LI-25), verify that timing margins in the original design are met across voltage/temperature variations. Programming voltages (typically 12-13 V VPP) must be applied correctly per the programming algorithm to avoid damaging the EPROM cells.
コンプライアンス情報
Original EP610 family predates widespread RoHS compliance requirements. RoHS and lead-free status not specified in verified web data; contact Rochester Electronics for current compliance documentation. AEC-Q100 not applicable - this is a legacy programmable logic device, not an automotive-qualified part.
