EP910LI-30T - 24-Macrocell Classic EPLD, 30ns, PQCC-44 | Altera
部品番号: EP910LI-30T ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $107.66 | $107.66 |
| 10 | $96.89 | $968.90 |
| 100 | $86.13 | $8,613.00 |
| 500 | $75.36 | $37,680.00 |
| 1,000 | $64.59 | $64,590.00 |
EP910LI-30T 概要
What is a Classic EPLD? A Classic Erasable Programmable Logic Device (EPLD) is a type of programmable logic IC that combines AND/OR arrays with user-programmable macrocells, enabling the replacement of multiple discrete SSI/MSI logic gates with a single re-programmable device. EPLDs sit at the lower end of the programmable logic hierarchy below CPLDs and FPGAs, offering non-volatile (UV-erasable) configuration, predictable timing, and fast pin-to-pin propagation delays - ideal for glue-logic, state-machine, and bus-Interface applications.
The EP910LI-30T delivers 24 macrocells, 10 dedicated input pins, 24 I/O pins (bidirectional), and operates over the industrial temperature range of -40°C to +85°C. It is fabricated on advanced CMOS technology, providing high-speed, low-power logic integration with tPD of 30 ns, tCO of 20 ns, and fMAX compatible with high-speed control logic. The device is housed in a J-leaded PQCC-44 surface-mount package.
Architecturally, the EP910 uses a sum-of-products PLA structure feeding registered output macrocells, with each macrocell offering product-term allocation, output polarity control, and a flip-flop. Programming is performed via a standard EPROM programmer using the Altera Logic Programmer or compatible tools.
Typical applications include bus-interface glue logic, state-machine replacement of discrete 74LS/74HC logic, address decoding in microprocessor systems, and timing-control circuits in industrial controllers. Designers often choose the EP910 family when non-volatile configuration, deterministic timing, and high I/O count in a small plastic package are required.
When designing with this device, note that the PQCC-44 footprint requires socketed or reflow assembly; ensure proper handling of UV-erasable windowed versions if reprogramming is needed. For modern designs, verify that software tools (Altera MAX+PLUS II legacy support) are still accessible in your workflow.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the original Altera datasheet.
ドロップイン代替品: EP910LI-30T — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP910LI-30T （同一形状・フットプリント） — 相違点: Supply Voltage (VCC), Package, Propagation Delay (tPD), Family, Mounting Type.
クイック比較ツール — 並列比較する代替部品を選択:
EP910LI-30
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$49.5 / 個
データシートを見る →EP910LC-30T
✅ ドロップイン✓ 在庫あり
$7.1 / 個
データシートを見る →EP910LC44-30T
✅ ドロップイン✓ 在庫あり
$9.75 / 個
データシートを見る →EP910LC-30
✅ ドロップイン✓ 在庫あり
$22.5 / 個
データシートを見る →EP910LI-20T
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$21 / 個
データシートを見る →EP910LI-30T 最大定格＆電気的特性
| Family | Altera Classic EPLD |
| Number of Macrocells | 24 |
| Usable Gates | 450 |
| Propagation Delay (tPD) | 30 ns |
| Dedicated Inputs | 10 |
| I/O Pins | 24 |
| パッケージ | PQCC-44 (J-lead) |
| 動作温度 | -40C to +85C (Industrial) |
| Technology | CMOS, UV-erasable |
| 実装タイプ | Surface Mount |
| Programming Method | EPROM (UV-erasable) via Altera Logic Programmer |
EP910LI-30T ピン構成
| ピン 1 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 2 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 3 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 4 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 5 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 6 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 7 | GND — Ground |
| ピン 8 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 9 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 10 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 11 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 12 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 13 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 14 | INPUT — Dedicated input pin |
| ピン 15 | INPUT — Dedicated input pin |
| ピン 16 | INPUT — Dedicated input pin |
| ピン 17 | INPUT — Dedicated input pin |
| ピン 18 | INPUT — Dedicated input pin |
| ピン 19 | GND — Ground |
| ピン 20 | INPUT — Dedicated input pin |
| ピン 21 | INPUT — Dedicated input pin |
| ピン 22 | INPUT — Dedicated input pin |
| ピン 23 | INPUT — Dedicated input pin |
| ピン 24 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 25 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 26 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 27 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 28 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 29 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 32 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 33 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 34 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 35 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 36 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 37 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 38 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 39 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 40 | I/O — Macrocell I/O pin (bidirectional) |
| ピン 41 | INPUT/CLK — Dedicated input / Global clock |
| ピン 42 | INPUT/CLR — Dedicated input / Global clear |
| ピン 43 | VCC — Supply voltage |
| ピン 44 | VCC — Supply voltage |
主な用途
EP910LI-30T の用途: 6 件s: Microprocessor Bus Interface Glue Logic, State Machine Replacement for 74LS/74HC Logic, Address Decoding in Microprocessor Systems, Industrial Control Timing Circuits, Legacy Peripheral Replacement Logic, Prototyping Platform for Glue Logic.
Microprocessor Bus Interface Glue Logic
The EP910LI-30T is well-suited to microprocessor bus-interface glue logic, where its 24 macrocells and 30 ns tPD can replace multiple 74LS245/74LS244 buffers and address-decoder packages. With 10 dedicated inputs and 24 bidirectional I/O pins, the device can decode address lines, generate chip-selects for memory and peripherals, and implement bus-control state machines in a single PQCC-44 package. The industrial -40°C to +85°C temperature range makes the part appropriate for embedded SBCs and industrial controllers. Designers typically pair the EP910LI-30T with a 16- or 32-bit microcontroller to consolidate 5-10 discrete logic packages into one programmable device, reducing PCB area and BOM cost.
おすすめ
State Machine Replacement for 74LS/74HC Logic
The EP910LI-30T can replace 4-8 packages of 74LS/74HC flip-flops, decoders, and multiplexers when implementing small to medium state machines. Each macrocell provides a D flip-flop with product-term clocking and clear, allowing sequential logic to be expressed directly in the AND/OR array. The 30 ns tPD supports state-machine clock rates up to ~10 MHz, sufficient for most industrial-control, instrumentation, and serial-protocol sequencing tasks. The non-volatile UV-erasable configuration means the state machine starts running at power-on without an external boot device - a key advantage over SRAM-based FPGAs in safety-critical or deterministic applications.
おすすめ
Address Decoding in Microprocessor Systems
Address decoding for memory and peripheral chip-select signals is a classic application for the EP910LI-30T, leveraging its 10 dedicated inputs to monitor address and control lines (A0-A7 plus RD/WR). The 24 I/O pins can drive up to 24 chip-select outputs, replacing an entire 74LS138/74LS139 decoder tree in one package. With 30 ns tPD, the part adds negligible address-to-chip-select delay, allowing it to sit between the CPU and memory without impacting access-time budgets. Designers can reprogram the decoder map via UV erasure when memory layouts change, providing hardware reuse across product variants without board respins.
おすすめ
Industrial Control Timing Circuits
The EP910LI-30T's industrial -40°C to +85°C temperature range and 30 ns deterministic timing make it appropriate for industrial-control timing circuits such as conveyor sequencers, valve controllers, and machine-tool interfaces. The 24 macrocells can encode timer chains, watchdog logic, and interlock sequences without external counters or one-shots. The PQCC-44 J-lead package withstands industrial vibration and thermal cycling better than ceramic-windowed DIPs. Engineers use the EP910LI-30T in PLCs and stand-alone controllers where non-volatile configuration and predictable timing are required, and where modern CPLD software tools are not available in legacy workflows.
おすすめ
Legacy Peripheral Replacement Logic
When modernizing equipment that uses now-discrete 74LS logic boards, the EP910LI-30T can consolidate 5-15 logic packages into a single PQCC-44 EPLD, reducing board size and improving reliability through fewer solder joints. The 450 usable gates cover typical peripheral tasks like serial-port encoding (UART bit-banging), parallel-port handshaking, and interrupt-controller glue. Because the device is non-volatile, it boots instantly at power-on - critical for legacy military, aerospace, and medical equipment where deterministic startup behavior is mandated. Rochester Electronics supplies traceable date-coded units for these long-lifecycle applications.
おすすめ
Prototyping Platform for Glue Logic
Engineering labs and university courses use the EP910LI-30T as a UV-erasable prototyping platform for teaching programmable logic concepts and for rapid iteration of glue-logic designs. Designers can compile a design, program the device with an Altera Logic Programmer, and verify operation in-circuit - then UV-erase and reprogram in minutes. The 30 ns tPD and 24 macrocells are sufficient for educational examples like ALU glue, simple CPU decode, and I/O expansion. The PQCC-44 package fits standard 44-pin PLCC sockets, making the part easy to swap between prototypes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP910LI-30T — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP910LI-30 | EP910LC-30T | EP910LC44-30T | EP910LC-30 | EP910LI-20T |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQCC-44 | PQCC-44 - same | PQCC-44 - same | PQCC-44 - same | PQCC-44 - same | PQCC-44 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| Propagation Delay (tPD) | 30 ns | 30 ns | 30 ns | 30 ns | 30 ns | 20 ns (-33%) |
| Temperature Range | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
| Packaging | Tape & Reel | Tray | Tape & Reel | Tape & Reel | Tray | Tape & Reel |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Industrial temperature range option （vs EP910LC-30T)
- Tape and Reel packaging for SMT （vs EP910LI-30)
- Balanced speed/cost in 30ns tier （vs EP910LI-20T)
設計ノート
The EP910LI-30T PQCC-44 J-lead package requires careful PCB land-pattern design per JEDEC MO-047. Recommended pad dimensions are 0.040 x 0.085 inch with 0.050 inch pitch. Use a socket (e.g., 44-pin PLCC socket, 3M 8444-21B1-RK or equivalent) for prototyping to allow UV-erase and reprogram cycles; for production, reflow solder with no-clean flux. Ensure adequate thermal relief on VCC/GND planes because the J-leads provide limited thermal conduction. Place decoupling capacitors (0.1 uF ceramic per VCC pin) within 100 mils of the package leads.
The Altera Classic EPLD family is UV-erasable; windowed ceramic DIP variants (e.g., EP910LC-12 ceramic) are required if you need to reprogram after solder assembly. Once a plastic PQCC-44 part like the EP910LI-30T is soldered, it cannot be erased - it is one-time-programmable (OTP) in plastic. Ensure your design is fully verified in a windowed programmer or socketed prototype before committing the plastic part to production. Additionally, MAX+PLUS II software is end-of-life - plan for legacy Windows XP/7 virtual-machine support in your design flow.
When using the EP910LI-30T as a bus decoder or glue-logic device on high-speed microprocessor buses (>25 MHz), observe 30 ns tPD through the device. The macrocell output drive is limited (typically 24 mA IOL per the family datasheet); add external bus drivers (74LS245/74LVC245) if driving heavily-loaded backplanes or long traces. Use the dedicated clock/clear pins (pins 41/42 per the PQCC-44 pinout) rather than routed clocks for predictable timing. Keep I/O traces short and use ground-pour shielding to minimize crosstalk in dense designs.
コンプライアンス情報
RoHS, REACH, and lead-free status not explicitly confirmed in the provided data. Rochester Electronics offers both RoHS-compliant and legacy SnPb finishes depending on date code. AEC-Q100 not applicable - this is a logic device, not an automotive-qualified IC.
