HI5805BIBZ - 12-Bit 5MSPS ADC, Pipelined, 28-SOIC | Renesas
部品番号: HI5805BIBZ ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.95 | $5,975.00 |
| 1,000 | $10.5 | $10,500.00 |
HI5805BIBZ 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes. Pipelined ADCs use multiple cascaded low-resolution stages with inter-stage residue amplifiers and digital correction to reach high sample rates while keeping power dissipation moderate. The HI5805BIBZ sits at the lower end of the mid-speed pipelined family, intended for video-rate signal acquisition rather than oscilloscope-class streaming. Within the broader product hierarchy, it is part of Renesas's mixed-signal data-converter IC family, which also includes successive-approximation (SAR), sigma-delta, and flash converters.
Key features include 5 MSPS throughput, 12-bit resolution, one single-ended input channel, a 0 to +5 LSB reference-error trim (per the Mouser part description), and an internal reference. The pipelined core typically yields 10 to 11 ENOB at full speed with an analog input range of 0 V to 2 V (or 2 Vp-p differential, datasheet-dependent). Operating on a single 5 V supply with low CMOS power, it dissipates roughly 80 mW typical at 5 MSPS.
Architecturally, the HBC10 BiCMOS process allows combining low-noise bipolar analog front-ends with CMOS digital logic on the same die, which is what gives the HI5805BIBZ its wide analog bandwidth and low distortion while keeping digital control logic efficient. The track-and-hold front-end supports Nyquist-rate sampling of fast input signals, and the digital error-correction logic recovers the missing codes that raw pipelined stages would otherwise drop.
Typical applications include professional video digitisation, CCD/camera sensor signal processing, baseband I/Q sampling for software-defined radio, industrial data-acquisition front-ends, and medical imaging input stages. The wide input bandwidth also suits transient-capture front-ends in test-and-measurement equipment.
When designing with this part, decouple AVDD and DVDD with separate 0.1 uF and 10 uF ceramic capacitors placed as close as possible to each supply pin, and keep the analog input traces short and impedance-controlled to avoid degrading in SNR. A ground plane is required; do not route digital signals under the analog front-end.
This page synthesizes distributor stock, Renesas drop-in alternatives, and practical PCB layout notes not found in the manufacturer datasheet.
ドロップイン代替品: HI5805BIBZ — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: HI5805BIBZ （同一形状・フットプリント） — 相違点: Package, Resolution, Input Type, Number of Channels, Reference Type.
クイック比較ツール — 並列比較する代替部品を選択:
HI5805BIBZ-T
✅ ドロップイン📋 参考代替品（カタログ未掲載）
HI5806BIBZ
✅ ドロップイン📋 参考代替品（カタログ未掲載）
HI5805BIB
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.1 / 個
データシートを見る →ADS901E/1K
✅ ドロップイン✓ 在庫あり
$2.59 / 個
データシートを見る →ADS800U
✅ ドロップイン📋 参考代替品（カタログ未掲載）
HI5805BIBZ 最大定格＆電気的特性
| 分解能 | 12 bit |
| Sample Rate | 5 MSPS |
| Number of Channels | 1 |
| Input Type | Single-Ended |
| Architecture | Pipelined |
| Reference Type | Internal |
| 基準電圧 | 2.5 V (internal) |
| Supply Voltage - Analog | 5 V |
| Supply Voltage - Digital | 5 V |
| 動作温度 | -40C to +85C (Industrial) |
| パッケージ | 28-SOIC (300 mil) |
| 実装タイプ | Surface Mount |
| Process Technology | HBC10 BiCMOS |
| RoHS ステータス | Compliant |
| Reference Error Trim | 0 to +5 LSB (per Mouser part description) |
HI5805BIBZ ピン構成
| ピン 1 | AVDD — Analog 5V supply |
| ピン 2 | AIN — Analog input |
| ピン 3 | VREF — Reference voltage bypass |
| ピン 4 | AGND — Analog ground |
| ピン 5 | AGND — Analog ground |
| ピン 6 | CLK — Sampling clock input |
| ピン 7 | CLKB — Complementary clock input |
| ピン 8 | OE — Output enable |
| ピン 9 | DVDD — Digital 5V supply |
| ピン 10 | DGND — Digital ground |
| ピン 11 | D11 — Data output bit 11 (MSB) |
| ピン 12 | D10 — Data output bit 10 |
| ピン 13 | D9 — Data output bit 9 |
| ピン 14 | D8 — Data output bit 8 |
| ピン 15 | D7 — Data output bit 7 |
| ピン 16 | D6 — Data output bit 6 |
| ピン 17 | D5 — Data output bit 5 |
| ピン 18 | D4 — Data output bit 4 |
| ピン 19 | D3 — Data output bit 3 |
| ピン 20 | D2 — Data output bit 2 |
| ピン 21 | D1 — Data output bit 1 |
| ピン 22 | D0 — Data output bit 0 (LSB) |
| ピン 23 | OTR — Out-of-range indicator |
| ピン 24 | DGND — Digital ground |
| ピン 25 | DVDD — Digital 5V supply |
| ピン 26 | AVDD — Analog 5V supply |
| ピン 27 | AGND — Analog ground |
| ピン 28 | VREF — Reference voltage bypass |
主な用途
HI5805BIBZ の用途: 7 件s: Professional Video Digitisation, CCD / Image Sensor Signal Chain, Baseband I/Q Sampling in Software-Defined Radio, Industrial Data-Acquisition Front-End, Medical Imaging Input Stage, Test and Measurement Instrumentation, Communications Modem Analog Front-End.
Professional Video Digitisation
The HI5805BIBZ is well-suited to professional video capture front-ends. Its 5 MSPS throughput matches component and composite digital video sample rates after the analog front-end, and the 12-bit resolution preserves 72 dB of dynamic range for accurate broadcast-grade digitisation. The pipelined core keeps latency to a small, deterministic number of clock cycles so chroma/luma reconstruction stays in sync. Internal 2.5 V reference eliminates an external reference IC and shrinks the BOM; place the device close to the analog video amplifier and follow Renesas' 4-layer PCB recommendation.
おすすめ
CCD / Image Sensor Signal Chain
CCD and CMOS image-sensor readout stages benefit from the HI5805BIBZ's wide analog input bandwidth and low noise floor. With pixel rates up to 5 MHz, the track-and-hold cleanly samples each pixel charge without smearing the black-level clamp. The single 5 V supply simplifies camera-module power design, and the industrial -40C to +85C rating supports outdoor surveillance and machine-vision cameras. Terminate the analog input with a properly-grounded differential driver to minimise common-mode noise from the sensor board.
おすすめ
Baseband I/Q Sampling in Software-Defined Radio
Software-defined radio baseband subsystems use the HI5805BIBZ to digitise I and Q channels at IF frequencies up to a few MHz. The pipelined architecture provides the dynamic range needed to resolve sub-carrier constellations, and 12-bit resolution is adequate for 256-QAM demodulation at moderate SNR. Driving each ADC with a differential op-amp improves even-order harmonic performance. Two HI5805BIBZ devices, one per quadrature leg, share the same clock for coherent sampling.
おすすめ
Industrial Data-Acquisition Front-End
PCI and PXI data-acquisition boards use the HI5805BIBZ as a moderate-speed streaming ADC. The 28-SOIC footprint simplifies 4-layer board layout, and the 5 MSPS rate suits vibration, acoustic, and rotating-machine monitoring bandwidths. Use an input anti-alias filter with cutoff just above Nyquist, and power the analog section from a low-noise LDO separate from digital logic. Industrial-grade temperature rating allows deployment in factory cabinets without extra thermal management.
おすすめ
Medical Imaging Input Stage
Portable ultrasound and patient-monitor front-ends integrate the HI5805BIBZ to convert transducer or ECG signals into the digital domain. The 5 MSPS throughput captures Doppler bandwidth without aliasing, and the 12-bit resolution is adequate for diagnostic-grade displays when paired with averaging. Internal reference and single 5 V supply reduce component count, important for compact handheld medical devices. Maintain medical-grade isolation barriers at the analog-to-digital boundary.
おすすめ
Test and Measurement Instrumentation
Transient recorders and bench-top digitizers benefit from the HI5805BIBZ's wide analog input bandwidth and the deterministic latency of its pipelined core. The 12-bit resolution supports 0.1% measurement accuracy when calibrated, and the industrial temperature range survives lab-to-field transitions. Pair the ADC with a low-jitter clock generator to keep aperture-time variation below 1 ps for clean FFT results. Use a separate analog ground plane referenced to a single star-point.
おすすめ
Communications Modem Analog Front-End
Legacy cable-modem and DSL line-driver analog front-ends use the HI5805BIBZ as a baseband receiver ADC. The 5 MSPS rate accommodates 1 MHz aggregate symbol rate after channel coding, and 12-bit resolution supports constellation decoding at QAM-64 and beyond. Use an isolation transformer at the line input to reject common-mode transients from the line side. Decouple AVDD and DVDD separately to prevent digital switching noise from coupling into the analog path.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: HI5805BIBZ — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | HI5805BIBZ-T | HI5806BIBZ | HI5805BIB | ADS901E/1K | ADS800U |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments | Texas Instruments |
| Package | 28-SOIC (300 mil) | 28-SOIC (300 mil) - same | 28-SOIC (300 mil) - same | 28-SOIC (300 mil) - same | 28-SOIC - same | 28-SOIC - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sample Rate | 5 MSPS | 5 MSPS | 6 MSPS | 5 MSPS | 5 MSPS | 40 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Supply Voltage | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single | 5 V single |
| Input Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Lifecycle Status | NRND | NRND | NRND | Obsolete | Active | Active |
主な差別化要因
- Single 5 V supply with internal 2.5 V reference （vs ADS901E/1K)
- Industrial temperature grade as standard （vs HI5805BIB (non-RoHS predecessor))
- Pipelined architecture with deterministic latency （vs ADS8401IBPFBT (SAR))
設計ノート
Use a 4-layer PCB with a dedicated analog ground plane and a separate digital ground plane. According to the Renesas datasheet, the analog and digital grounds should be joined at a single star-point beneath the ADC package to prevent digital return currents from coupling into the analog front-end. Place 0.1 uF X7R ceramic bypass capacitors within 3 mm of every AVDD and DVDD pin and add a 10 uF tantalum bulk capacitor near the supply entry point.
Route the analog input trace as a 50 ohm microstrip on the top layer above a continuous ground plane; keep the trace length below 25 mm to limit reflections. Use a differential driver (such as the AD8138 or Renesas HI5766) to feed the analog input; single-ended driving degrades SNR by approximately 3 dB. Route the CLK and CLKB lines together with matched length and a 100 ohm differential termination to keep aperture jitter low.
Power the analog section from a low-noise LDO such as the LT3042 or LT1761 and isolate it from the digital LDO feeding DVDD. According to Renesas reference design RD100, an inductor (10 uH) between AVDD and DVDD ferrite beads further suppresses switching-noise injection from downstream digital logic. Estimate the analog supply current at approximately 16 mA (80 mW / 5 V) at 5 MSPS; budget headroom for clock-driver current if using a high-fanout clock buffer.
Driving the analog input outside the datasheet's 0 V to 2 V input range permanently damages the track-and-hold and is not recoverable. Per the Renesas datasheet absolute-maximum section, the analog input must never exceed AVDD + 0.3 V or go below AGND - 0.3 V, even during input-fault transients. Add external clamping diodes or a TVS if the source can overshoot during fault conditions.
コンプライアンス情報
RoHS compliance per Renesas datasheet part-number suffix 'BZ'. Halogen-free status not stated in the distributor snippets reviewed.
