LAN91C113-NU - 10/100 Ethernet MAC/PHY | Microchip
部品番号: LAN91C113-NU ✓ 生産中LAN91C113-NU 概要
An Ethernet MAC, or Media Access Control, manages frame transmission, reception, addressing, and access to the physical network medium. A PHY implements the physical signaling layer between the MAC and a twisted-pair cable. The LAN91C113 integrates both functions into one controller, reducing board area and external PHY count compared with a separate MAC and Ethernet transceiver design.
The controller supports 10Base-T and 100Base-TX operation over a 16-bit parallel MII. This combination suits embedded systems that already have a host processor with a compatible parallel bus but do not include an Ethernet PHY. Integration can reduce board routing, connector requirements, and the number of components requiring firmware and driver support.
The LAN91C113-NU belongs to the Ethernet interface IC and network interface controller hierarchy. Unlike a PCI-based Ethernet card, the parallel MII architecture connects directly to processor logic rather than a host peripheral bus. The 3.3 V operating supply is compatible with modern embedded processor systems, although the complete design must also satisfy the voltage requirements of attached memory, magnetics, and physical-layer circuitry.
Typical applications include industrial monitoring equipment, building automation controllers, embedded test equipment, industrial gateways, and compact network appliances. A typical implementation places the controller and an Ethernet jack with integrated magnetics on the same PCB, connects the host processor to the MII signals, and configures the MAC and PHY through the device’s control interface.
Design should begin with the manufacturer’s reference schematic and signal-integrity guidance. Route the parallel MII clock and data signals as a controlled-length group, provide the required decoupling, and follow the recommended magnetics and impedance-termination layout. Confirm that the host processor’s MII timing, voltage levels, interrupt requirements, and software driver support match the controller before committing the PCB layout.
This page consolidates the product identity, package information, application guidance, comparison criteria, and practical integration considerations engineers need when evaluating the LAN91C113-NU for a 10/100 Ethernet design. Use the Request a Quote form on this page for current commercial availability, packaging, lead time, and sourcing support.
ドロップイン代替品: LAN91C113-NU — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LAN91C113-NU （同一形状・フットプリント） — 相違点: Host Interface, Device Type, Ethernet Speed, Lead-Free Status, Package.
LAN91C113
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LAN91C113-NU 仕様
| Product Type | 10/100 Ethernet single-chip MAC and PHY controller |
| Ethernet Speed | 10/100 Mb/s |
| Supported Physical Media | 10Base-T and 100Base-TX |
| Host Interface | 16-bit parallel MII |
| Bus Architecture | Non-PCI parallel interface |
| Operating Supply | 3.3 V |
| パッケージ | 128-pin TQFP, 14 x 14 mm |
| ピン数 | 128 pins |
| 実装タイプ | Surface mount |
| Integrated PHY | Yes |
| Integrated MAC | Yes |
| Media Interface | MII |
| データバス幅 | 16 bits |
| Physical Layer Standard | IEEE 802.3 10/100 Ethernet |
| Maximum Link Rate | 100 Mb/s |
LAN91C113-NU 128-pin tqfp, 14 x 14 mm ピン配置ガイド
LAN91C113-NU (128-pin tqfp, 14 x 14 mm パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: LAN91C113-NU.
詳細は データシート をご参照ください。
主な用途
LAN91C113-NU の用途: 6 件s: Industrial Monitoring Controller, Building Automation Gateway, Embedded Test and Measurement Equipment, Industrial Network Appliance, Embedded HMI and Operator Panel, Compact Control System.
Industrial Monitoring Controller
The LAN91C113-NU fits industrial monitoring equipment that must report sensor, process, and alarm data over a 10/100 Mb/s Ethernet network. Its integrated MAC and PHY reduce the component count compared with a separate Ethernet MAC and transceiver, while the 16-bit MII provides a direct connection to a compatible embedded processor. The 3.3 V supply is suitable for many modern embedded platforms. Designers should align MII timing with the processor clock domain, provide the manufacturer-recommended magnetic isolation and termination, and validate network behavior under sustained traffic and electrical-noise conditions.
おすすめ
Building Automation Gateway
The LAN91C113-NU can provide wired Ethernet connectivity in building automation controllers, room controllers, and access-control gateways. Combining a 10/100 Mb/s MAC with an integrated PHY simplifies the network path while retaining a parallel MII interface for the embedded host. The controller’s 3.3 V operation fits processor systems designed around modern low-voltage logic. In this application, robust magnetics, compliant board layout, firmware restart behavior, and link-up timing are more important than maximizing throughput beyond the 100 Mb/s Ethernet limit.
おすすめ
Embedded Test and Measurement Equipment
The LAN91C113-NU is appropriate for embedded test instruments that must transfer results, logs, or control commands through a 10 Mb/s or 100 Mb/s Ethernet connection. Its integrated MAC and PHY simplify the interface between a parallel processor subsystem and a physical network, and the 16-bit MII supports direct attachment without a PCI bus. For measurement products, separate the analog or sensitive signal paths from digital Ethernet routing, keep switching regulators and MII clocks away from sensitive inputs, and verify that the selected Ethernet jack provides the isolation and filtering required by the design.
おすすめ
Industrial Network Appliance
The LAN91C113-NU can serve as the primary 10/100 Ethernet interface in a compact industrial gateway, protocol converter, serial-to-Ethernet appliance, or embedded network server. Integrating the MAC and PHY reduces the number of high-speed digital routing paths on a constrained PCB, while the non-PCI MII arrangement works well with processors that expose an asynchronous parallel Ethernet interface. Keep the controller close to the Ethernet connector and magnetics, follow the manufacturer reference layout, and provide clean supply decoupling to minimize link errors and packet retransmissions.
おすすめ
Embedded HMI and Operator Panel
A human-machine interface can use the LAN91C113-NU for wired data exchange, remote configuration, and supervisory control over a 10/100 Mb/s Ethernet network. The integrated MAC and PHY avoid a separate Ethernet transceiver, and the 16-bit MII offers a straightforward connection to compatible application processors. The 100 Mb/s maximum Ethernet rate is sufficient for typical configuration, logging, and supervisory workloads. Confirm processor-side driver support, interrupt handling, and memory alignment before hardware design, then validate recovery after link interruption or power-cycle events.
おすすめ
Compact Control System
The LAN91C113-NU is suitable for compact controllers that exchange commands and status with supervisory software over Ethernet. Its 10/100 Mb/s MAC and PHY handle the network protocol below the application layer, allowing the host processor to focus on control tasks. The 3.3 V supply and 128-pin TQFP package support integration into embedded electronics, but the parallel MII requires careful clock, data, and control routing. Use the manufacturer reference design to establish trace geometry, magnetics placement, termination, and grounding, particularly in equipment containing motors, relays, or switching power converters.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LAN91C113-NU — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LAN91C113 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Package | 128-TQFP (14x14) | 128-TQFP (14x14) |
| Product Type | 10/100 Ethernet single-chip MAC and PHY controller | 10/100 Ethernet single-chip MAC and PHY controller |
| Ethernet Speed | 10/100 Mb/s | 10/100 Mb/s |
| Host Interface | 16-bit parallel MII | 16-bit parallel MII |
| Bus Architecture | Non-PCI | Non-PCI |
| Operating Supply | 3.3 V | 3.3 V |
| Integrated PHY | Yes | Yes |
| Physical Media | 10Base-T and 100Base-TX | 10Base-T and 100Base-TX |
主な差別化要因
- Integrated MAC and PHY reduce external network-interface components （vs KSZ8721SL-TR)
- Direct parallel processor interface avoids a PCI dependency （vs Intel i8255x)
- Single-chip 10/100 Ethernet integration supports embedded designs （vs Marvell 88E1510)
設計ノート
Place the LAN91C113-NU, Ethernet magnetics, and RJ45 connector according to the manufacturer reference layout. Keep the MII clock and associated data traces tightly controlled, minimize stubs, provide a continuous reference plane, and avoid crossing high-current switching paths. The parallel MII signals should be routed as a coordinated group so that timing margins are not reduced by inconsistent trace lengths or plane transitions.
Apply the manufacturer’s recommended supply decoupling directly at the device power pins and isolate the Ethernet section from noisy switching nodes. Verify that the 3.3 V rail remains within the operating limits across temperature and load. Because Ethernet link integrity can be affected by supply ripple, use a low-noise supply path and check the power-consumption and thermal conditions of the complete controller, magnetics, and communications circuitry.
Do not substitute the base LAN91C113 family designation without confirming the ordering suffix, package, temperature grade, and lifecycle status. A similarly named controller does not establish MII timing compatibility. Before releasing a replacement, compare pin names and directions, power pins, reset and management-interface behavior, PHY strap configuration, interrupt behavior, clock requirements, and host software support. This prevents a nominal package match from becoming an electrical or software incompatibility.
コンプライアンス情報
Compliance declarations must be confirmed against the exact LAN91C113-NU ordering code and current manufacturer documentation.
