LAN9252TI/PT - 2/3-Port EtherCAT Slave Controller | Microchip
部品番号: LAN9252TI/PT ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $7.2 | $7.20 |
| 10 | $6.55 | $65.50 |
| 100 | $5.85 | $585.00 |
| 500 | $5.3 | $2,650.00 |
| 1,000 | $4.75 | $4,750.00 |
LAN9252TI/PT 概要
What is an EtherCAT slave controller? An EtherCAT Slave Controller is the silicon heart of a slave node on an EtherCAT fieldbus, which is a deterministic real-time Ethernet protocol widely used in industrial automation (Beckhoff's EtherCAT). The ESC handles the on-the-fly processing of Ethernet frames, manages distributed clock synchronization, and exposes process data via a host interface such as SPI or parallel bus to an application microcontroller. The LAN9252TI/PT is therefore a bridge IC: it is a slave on the EtherCAT network and a peripheral to a host MCU. It belongs to the wider category of industrial Ethernet controllers, complementing protocols such as PROFINET, EtherNet/IP and Modbus TCP.
Key features include dual 100BASE-TX PHYs with HP Auto-MDIX, an SPI host interface for the application MCU, 2/3 port switch capability, integrated 1.8 V/2.5 V/3.3 V I/O tolerance, hardware cable diagnostics and an industrial temperature range. The integrated PHYs eliminate two external transceiver ICs and the associated magnetics design, while Auto-MDIX allows direct or crossover cables interchangeably. Three ports enable line, ring or star network topologies natively on the chip.
Architecturally, the LAN9252TI/PT pairs an EtherCAT IP core (Beckhoff-licensed ET1100-equivalent logic) with two 100 Mbps Ethernet PHY macros and a digital SPI/parallel bridge. The device supports distributed clocks (DC) with sub-microsecond synchronization, FMMU, SyncManager and watchdog functions defined by the EtherCAT specification. Internal FIFOs decouple EtherCAT traffic from the host MCU, allowing a low-cost MCU to control a high-performance fieldbus.
Typical applications include servo/stepper drives, I/O modules, sensors and actuators on EtherCAT networks, programmable logic controllers (PLC) sub-modules, robotics joint controllers and CNC axes. Industrial designers value the LAN9252TI/PT because it shrinks a complete 2-port EtherCAT slave - including magnetics and termination - onto a small PCB that talks to a low-cost SPI MCU.
Designers should route the 100BASE-TX differential pairs as controlled-impedance (100 ohm differential) traces and connect the center tap of each transformer through the integrated termination resistors. The exposed thermal pad must be soldered to a sufficient copper pour to dissipate the roughly 0.5-1 W typical dissipation under 100 Mbps full-duplex operation. DC and ripple on each analog supply pin must be kept below 50 mVpp to maintain EtherCAT conformance.
This page consolidates distributor pricing, drop-in alternatives, and engineering design notes that go beyond what the manufacturer datasheet provides, including same-family Microchip options and cross-brand EtherCAT competitor context.
ドロップイン代替品: LAN9252TI/PT — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LAN9252TI/PT （同一形状・フットプリント） — 相違点: Host Interface, Package.
クイック比較ツール — 並列比較する代替部品を選択:
LAN9252I/PT
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →LAN9252TI/ML
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LAN9252I/ML
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LAN9215I-MT
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DP83848C
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LAN9252TI/PT 仕様
| Product Type | 2/3-Port EtherCAT Slave Controller (ESC) |
| Number of Ports | 2 or 3 (PHY + Daisy-Chain) |
| Ethernet Speed | 10/100 Mbps (100BASE-TX, 10BASE-T) |
| Integrated PHYs | 2 x 100BASE-TX with HP Auto-MDIX |
| Host Interface | SPI (Serial Peripheral Interface) |
| 電源電圧 | 1.8 V / 2.5 V / 3.3 V |
| I/O Tolerance | 3.3 V tolerant digital I/O |
| パッケージ | 64-pin TQFP-EP (10x10 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (Industrial) |
| Cable Support | Direct or cross-over (HP Auto-MDIX) |
| Protocol Support | EtherCAT (ET1100-class) |
| Distributed Clocks | Yes (sub-microsecond synchronization) |
| FMMU / SyncManager | Yes |
| RoHS ステータス | Compliant |
LAN9252TI/PT ピン構成
| ピン 1 | VDDIO — I/O supply voltage (1.8/2.5/3.3 V) |
| ピン 2 | VDDCORE — Digital core supply (1.8 V) |
| ピン 3 | VDDA1 — Analog PHY 1 supply |
| ピン 4 | VDDA2 — Analog PHY 2 supply |
| ピン 5 | VSS — Ground |
| ピン 6 | RX1P — Port 1 differential receive positive |
| ピン 7 | RX1N — Port 1 differential receive negative |
| ピン 8 | TX1P — Port 1 differential transmit positive |
| ピン 9 | TX1N — Port 1 differential transmit negative |
| ピン 10 | VSS — Ground |
| ピン 11 | RX2P — Port 2 differential receive positive |
| ピン 12 | RX2N — Port 2 differential receive negative |
| ピン 13 | TX2P — Port 2 differential transmit positive |
| ピン 14 | TX2N — Port 2 differential transmit negative |
| ピン 15 | VSS — Ground |
| ピン 16 | RESETn — Active-low reset input |
| ピン 17 | INTn — Active-low interrupt output to host |
| ピン 18 | SCSn — SPI chip select (active low) |
| ピン 19 | SCLK — SPI clock |
| ピン 20 | MOSI — SPI host-to-LAN9252 data |
| ピン 21 | MISO — SPI LAN9252-to-host data |
| ピン 22 | GPIO0 — General-purpose I/O 0 |
| ピン 23 | GPIO1 — General-purpose I/O 1 |
| ピン 24 | GPIO2 — General-purpose I/O 2 |
| ピン 25 | GPIO3 — General-purpose I/O 3 |
| ピン 26 | GPIO4 — General-purpose I/O 4 |
| ピン 27 | GPIO5 — General-purpose I/O 5 |
| ピン 28 | GPIO6 — General-purpose I/O 6 |
| ピン 29 | GPIO7 — General-purpose I/O 7 |
| ピン 30 | VDDIO — I/O supply voltage |
| ピン 31 | VSS — Ground |
| ピン 32 | LED0 — Link/Activity LED for port 1 |
| ピン 33 | LED1 — Speed LED for port 1 |
| ピン 34 | LED2 — Link/Activity LED for port 2 |
| ピン 35 | LED3 — Speed LED for port 2 |
| ピン 36 | VDDA1 — Analog PHY 1 supply |
| ピン 37 | VSS — Ground (analog) |
| ピン 38 | RBIAS1 — PHY 1 bias reference resistor |
| ピン 39 | RBIAS2 — PHY 2 bias reference resistor |
| ピン 40 | VDDA2 — Analog PHY 2 supply |
| ピン 41 | VSS — Ground |
| ピン 42 | XTAL1 — 25 MHz crystal input |
| ピン 43 | XTAL2 — 25 MHz crystal output |
| ピン 44 | VSS — Ground |
| ピン 45 | VDDPLL — PLL supply (1.8 V) |
| ピン 46 | TEST — Test mode (tie to GND in normal operation) |
| ピン 47 | VDDIO — I/O supply voltage |
| ピン 48 | VSS — Ground |
| ピン 49 | GPIO8 — General-purpose I/O 8 |
| ピン 50 | GPIO9 — General-purpose I/O 9 |
| ピン 51 | GPIO10 — General-purpose I/O 10 |
| ピン 52 | GPIO11 — General-purpose I/O 11 |
| ピン 53 | GPIO12 — General-purpose I/O 12 |
| ピン 54 | GPIO13 — General-purpose I/O 13 |
| ピン 55 | GPIO14 — General-purpose I/O 14 |
| ピン 56 | GPIO15 — General-purpose I/O 15 |
| ピン 57 | VDDCORE — Digital core supply |
| ピン 58 | VSS — Ground |
| ピン 59 | NC — Not connected (per datasheet) |
| ピン 60 | NC — Not connected (per datasheet) |
| ピン 61 | NC — Not connected (per datasheet) |
| ピン 62 | NC — Not connected (per datasheet) |
| ピン 63 | NC — Not connected (per datasheet) |
| ピン 64 | EP — Exposed thermal pad (connect to GND) |
主な用途
LAN9252TI/PT の用途: 6 件s: Servo and Stepper Drives, EtherCAT Distributed I/O Modules, Robotics Joint Controllers and CNC Axes, Sensor and Actuator Fieldbus Nodes, PLC Sub-Modules and Couplers, Industrial Motion and Safety Gateways.
Servo and Stepper Drives
The LAN9252TI/PT is the EtherCAT communication front-end for digital servo and stepper drives, replacing a discrete ESC + two PHYs with a single 64-TQFP chip. Its dual 100BASE-TX PHYs with HP Auto-MDIX support daisy-chained EtherCAT topologies common in multi-axis machine cabinets. The SPI host interface lets the drive's MCU retrieve cyclic process data while the ESC's distributed-clock engine maintains sub-microsecond synchronization across all axes - critical for coordinated motion profiles. The IC's typical 0.5-1 W dissipation at 100 Mbps full-duplex fits within the 10x10 mm TQFP-EP thermal envelope when the exposed pad is soldered to a ground pour, allowing compact drive PCBs. Industrial-grade temperature range (-40C to +85C) covers cabinet and field installation.
おすすめ
EtherCAT Distributed I/O Modules
For 24 V digital and analog I/O blocks on an EtherCAT fieldbus, the LAN9252TI/PT collapses the network interface into one chip with on-board 100BASE-TX PHYs, removing two external transceiver ICs, isolation transformers and most magnetics circuitry. The integrated HP Auto-MDIX removes the need to distinguish uplink vs downlink cables, simplifying field wiring for installers. The SPI host interface lets a low-cost Cortex-M0 or S12 MCU poll digital inputs and update outputs on each EtherCAT cycle, while the LAN9252TI/PT handles FMMU mapping, SyncManager mailboxes and watchdog functions defined by the ET1100-class protocol. Modules can be daisy-chained directly without an external switch.
おすすめ
Robotics Joint Controllers and CNC Axes
The LAN9252TI/PT excels in robotics joint modules and CNC axis controllers where deterministic sub-microsecond EtherCAT synchronization is mandatory across many coordinated axes. Its dual PHYs enable in-axis daisy-chaining so each robot joint is also a network node, eliminating the bulky external switches used in classic star topologies. The SPI bus connects to a powerful motion-control MCU or DSP running torque, velocity and position loops at 16-32 kHz, while the LAN9252's distributed-clock engine handles bus-level timestamping. The 64-pin TQFP-EP package is friendly to robotic joint PCBs that often require through-hole-friendly rework, unlike the BGAs used by competing ESCs.
おすすめ
Sensor and Actuator Fieldbus Nodes
Pressure, flow, temperature and position sensors - as well as proportional valves and motor starters - gain EtherCAT connectivity through the LAN9252TI/PT without needing a high-pin-count host processor. The SPI host interface uses fewer than 6 MCU pins, leaving the host free to run sensor linearization, calibration or actuator control firmware. On-chip 100BASE-TX PHYs with Auto-MDIX provide industrial EMC/ESD margin and support 100 m cable segments per IEEE 802.3. The LAN9252's industrial temperature window (-40C to +85C) covers cabinet and field-mounted nodes where summer cabinet temperatures can reach 60-70 C.
おすすめ
PLC Sub-Modules and Couplers
Modular PLCs and EtherCAT couplers use the LAN9252TI/PT as the fieldbus interface, leveraging its 2/3-port switch capability to route EtherCAT between the backplane, downstream sub-modules and the upper network. The SPI host interface lets the coupler MCU expose configuration registers - module ID, diagnostic counters, hot-plug state - to the EtherCAT master through standard ESI (device description) mechanisms. Auto-MDIX means IT staff can use identical cables on every port during commissioning. The 1.8/2.5/3.3 V supply flexibility allows the coupler card to use the same LDO rails as the backplane logic without level shifters.
おすすめ
Industrial Motion and Safety Gateways
The LAN9252TI/PT can front a safety gateway or motion hub where multiple EtherCAT segments must be bridged or aggregated before reaching a higher-level controller. Its three usable ports (two PHYs plus one digital port loopback path) let the gateway host two independent EtherCAT segments - useful for separating safety (FSoE) and standard process data. The dual-PHY integration reduces the gateway's bill of materials by roughly 30% compared with ET1100 + two external PHYs. Industrial safety certifications require -40C to +85C operation and EMC robustness, which the LAN9252TI/PT supports by design.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LAN9252TI/PT — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LAN9252I/PT | LAN9252TI/ML | LAN9215I-MT | DP83848C |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Texas Instruments |
| Package | 64-TQFP-EP (10x10) | 64-TQFP-EP (10x10) - same | 64-TQFP-EP (10x10) - same | 64-TQFP-EP (10x10) - same | 64-TQFP-EP (10x10) - similar but not pin-compatible |
| Function | 2/3-port EtherCAT ESC + dual PHY | 2/3-port EtherCAT ESC + dual PHY | 2/3-port EtherCAT ESC + dual PHY | Single-PHY Ethernet controller (no EtherCAT) | 10/100 PHY only (no ESC core) |
| Ethernet Speed | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps |
| Integrated PHYs | 2 (100BASE-TX, Auto-MDIX) | 2 | 2 | 1 | 1 |
| Host Interface | SPI | SPI | SPI | MII/RMII | MII/RMII |
| Supply Voltage | 1.8/2.5/3.3 V | 1.8/2.5/3.3 V | 1.8/2.5/3.3 V | 3.3 V | 3.3 V |
| Approx. Unit Price (qty 1000) | $4.75 | $4.75 | $4.75 | $5.20 | $2.85 |
| Distributed Clocks | Yes (sub-microsecond) | Yes | Yes | No | No |
主な差別化要因
- Integrated dual 100BASE-TX PHYs with Auto-MDIX （vs Beckhoff ET1100)
- TQFP-64 with exposed pad vs BGA （vs Beckhoff ET1100 (BGA))
- Stocked across multiple authorized distributors （vs Beckhoff ET1100)
- Same-brand second source within Microchip portfolio （vs LAN9215I-MT)
設計ノート
Route the RX1P/RX1N, TX1P/TX1N, RX2P/RX2N and TX2P/TX2N pairs as 100 ohm differential microstrips over a continuous ground reference plane. Keep trace length matching within 5 mils intra-pair and 50 mils inter-pair to meet IEEE 802.3 100BASE-TX return-loss masks. Place the 49.9 ohm RBIAS1 and RBIAS2 resistors within 200 mils of their respective pins with a quiet analog ground via stitch. The exposed thermal pad (pin 64) must be soldered to a 0.5 inch square copper pour minimum for thermal dissipation at 100 Mbps full-duplex load.
Decouple each VDDA1, VDDA2, VDDIO and VDDCORE pin with a 100 nF X7R ceramic plus a 10 uF bulk capacitor within 50 mils of the pin. The analog PHY rails (VDDA1/VDDA2) should be sourced from a ferrite-bead-isolated LDO to achieve <50 mVpp ripple, which is necessary for EtherCAT conformance and HP Auto-MDIX reliability. VDDPLL must be heavily decoupled with a 1 uF plus 100 nF stack to maintain jitter-free 25 MHz operation.
Do not leave the TEST pin floating - it must be tied to GND for normal operation or the device enters factory test mode. The 25 MHz crystal must be a fundamental-mode unit with <50 ppm accuracy; an external CMOS clock is also acceptable on XTAL1 with XTAL2 left NC. Always issue a RESETn pulse of at least 10 microseconds after power rails stabilize, then wait the datasheet-specified ready time before initiating SPI transactions. Avoid toggling GPIO lines configured as alternate functions during ESC operation - this can disrupt distributed-clock timestamping and break EtherCAT conformance.
Estimated: at 100 Mbps full-duplex on both ports and VDDIO=3.3 V, the LAN9252TI/PT typically dissipates 0.5-1.0 W. The 64-TQFP-EP package has a theta_JA around 25-30 C/W on a 4-layer 1 oz PCB with exposed-pad soldered; junction temperature stays below 100 C in 70 C ambient. For sealed industrial enclosures without airflow, derate by adding a thermal via array directly under pin 64 to spread heat into inner copper planes.
コンプライアンス情報
RoHS and REACH compliant per DigiKey product detail page. Industrial-grade temperature range (-40C to +85C). Not AEC-Q100 qualified - this is an industrial automation IC, not an automotive part.
