LTC2183CUP - 16-Bit 80Msps Dual ADC Low Power QFN-64 | Analog Devices
部品番号: LTC2183CUP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $108.85 | $108.85 |
| 10 | $98.5 | $985.00 |
| 100 | $89.2 | $8,920.00 |
| 500 | $82.4 | $41,200.00 |
| 1,000 | $78.6 | $78,600.00 |
LTC2183CUP 概要
A dual pipelined ADC is a converter architecture that uses multiple low-resolution stages in series, with each stage sampling and converting a portion of the input before passing residue to the next stage; digital error correction aligns the bits. Dual ADCs are commonly used in diversity receivers, I/Q demodulation, and medical imaging where two correlated channels must be digitized on the same clock edge. The LTC2183 family belongs to the broader converter IC category, sitting between analog front-end signal conditioning and downstream DSP/FPGA logic.
Key features include user-selectable LVDS / DDR LVDS / CMOS output modes, a parallel low-voltage CMOS port option, an SPI port for configuration, internal dither to improve small-signal linearity, and a clock duty-cycle stabilizer. Total power consumption is approximately 390 mW at 80 Msps, far below competing dual ADCs. Input range is 2 Vp-p (fully differential) with an internal PGA.
Typical applications include communications receivers, basestation diversity channels, I/Q demodulators, portable instrumentation, medical imaging front-ends, and non-destructive ultrasonic testing. The exposed-pad QFN-64 package enables low thermal resistance for sustained operation. When designing in the LTC2183CUP, pay close attention to differential input network design, layout of the clock tree, and decoupling strategy on both AVDD and DVDD rails to realize the full 76.8 dB SNR specification.
ドロップイン代替品: LTC2183CUP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2183CUP （同一形状・フットプリント） — 相違点: Package, SNR, Resolution, SFDR, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2185CUP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2184CUP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2180CUP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$41.72 / 個
データシートを見る →LTC2145CUP-12
✅ ドロップイン✓ 在庫あり
$26.4 / 個
データシートを見る →LTC2155CUP-12
✅ ドロップイン✓ 在庫あり
$44.25 / 個
データシートを見る →LTC2153CUJ-14
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LTC2183CUP 最大定格＆電気的特性
| 分解能 | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 80 Msps |
| Architecture | Pipelined |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 psRMS |
| Input Range | 2 Vp-p differential |
| Power Consumption | 390 mW at 80 Msps |
| Output Interface | Parallel CMOS / LVDS / DDR LVDS (selectable) |
| Configuration Interface | SPI |
| パッケージ | 64-QFN (UP) 9x9 mm with exposed pad |
| 動作温度 | 0C to +70C (C grade) |
| Supply Voltage AVDD | 1.8 V |
| Supply Voltage DVDD | 1.8 V (separate AVDD/DVDD) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (PBF suffix) |
| Internal Dither | Yes, user-selectable |
LTC2183CUP ピン構成
| ピン 1 | INA+ — Channel A positive differential input |
| ピン 2 | INA- — Channel A negative differential input |
| ピン 3 | INB+ — Channel B positive differential input |
| ピン 4 | INB- — Channel B negative differential input |
| ピン 5 | GND — Ground reference |
| ピン 6 | AVDD — Analog 1.8 V supply |
| ピン 7 | GND — Ground |
| ピン 8 | AVDD — Analog 1.8 V supply |
| ピン 9 | REF — Internal reference decoupling |
| ピン 10 | GND — Ground |
| ピン 11 | REFT — Reference top decoupling |
| ピン 12 | REFB — Reference bottom decoupling |
| ピン 13 | GND — Ground |
| ピン 14 | AVDD — Analog 1.8 V supply |
| ピン 15 | ENC+ — Encode clock positive input |
| ピン 16 | ENC- — Encode clock negative input |
| ピン 17 | GND — Ground |
| ピン 18 | AVDD — Analog 1.8 V supply |
| ピン 19 | OFA+ — Output format A+B adjustable |
| ピン 20 | GND — Ground |
| ピン 21 | CS — SPI chip select |
| ピン 22 | SCK — SPI serial clock |
| ピン 23 | SDI — SPI serial data input |
| ピン 24 | SDO — SPI serial data output |
| ピン 25 | OEB — Output enable B |
| ピン 26 | OEA — Output enable A |
| ピン 27 | MODE — Output mode select |
| ピン 28 | NC — Not connected |
| ピン 29 | NC — Not connected |
| ピン 30 | GND — Ground |
| ピン 31 | D0A — Channel A data bit 0 (LSB) |
| ピン 32 | D1A — Channel A data bit 1 |
| ピン 33 | D2A — Channel A data bit 2 |
| ピン 34 | D3A — Channel A data bit 3 |
| ピン 35 | D4A — Channel A data bit 4 |
| ピン 36 | D5A — Channel A data bit 5 |
| ピン 37 | D6A — Channel A data bit 6 |
| ピン 38 | D7A — Channel A data bit 7 |
| ピン 39 | D8A — Channel A data bit 8 |
| ピン 40 | D9A — Channel A data bit 9 |
| ピン 41 | D10A — Channel A data bit 10 |
| ピン 42 | D11A — Channel A data bit 11 |
| ピン 43 | D12A — Channel A data bit 12 |
| ピン 44 | D13A — Channel A data bit 13 |
| ピン 45 | D14A — Channel A data bit 14 |
| ピン 46 | D15A — Channel A data bit 15 (MSB) |
| ピン 47 | DCLKA — Channel A data clock |
| ピン 48 | FRAMA — Channel A frame output |
| ピン 49 | D0B — Channel B data bit 0 (LSB) |
| ピン 50 | D1B — Channel B data bit 1 |
| ピン 51 | D2B — Channel B data bit 2 |
| ピン 52 | D3B — Channel B data bit 3 |
| ピン 53 | D4B — Channel B data bit 4 |
| ピン 54 | D5B — Channel B data bit 5 |
| ピン 55 | D6B — Channel B data bit 6 |
| ピン 56 | D7B — Channel B data bit 7 |
| ピン 57 | D8B — Channel B data bit 8 |
| ピン 58 | D9B — Channel B data bit 9 |
| ピン 59 | D10B — Channel B data bit 10 |
| ピン 60 | D11B — Channel B data bit 11 |
| ピン 61 | D12B — Channel B data bit 12 |
| ピン 62 | D13B — Channel B data bit 13 |
| ピン 63 | D14B — Channel B data bit 14 |
| ピン 64 | D15B — Channel B data bit 15 (MSB) |
主な用途
LTC2183CUP の用途: 6 件s: Communications Diversity Receiver, Medical Imaging Front-End, Portable Test Instrumentation, Non-Destructive Testing Ultrasound, Software Defined Radio / I/Q Demodulation, Radar and Lidar Signal Acquisition.
Communications Diversity Receiver
The LTC2183CUP's dual simultaneous-sampling channels with 76.8 dB SNR and 90 dB SFDR make it ideal for cellular basestation diversity receivers. Both I and Q channels digitize on the same clock edge, eliminating channel-to-channel skew that would otherwise degrade demodulation. The 0.07 psRMS aperture jitter enables IF undersampling at high input frequencies, supporting multicarrier WCDMA/LTE signals. Power dissipation of 390 mW at 80 Msps suits thermally constrained outdoor radio units. LVDS output mode offers low-EMI routing to a downstream FPGA digital front-end over standard FR-4 PCB traces.
おすすめ
Medical Imaging Front-End
The LTC2183CUP suits ultrasound and portable medical imaging front-ends where dual-channel acquisition, low power, and small package size are critical. The 64-QFN (UP) 9x9 mm package enables compact transducer-array PCBs. Both channels digitize returning RF echoes simultaneously, preserving phase information used in beamforming. With 76.8 dB SNR the converter resolves small-amplitude echo returns in tissue, while 0.07 psRMS jitter preserves timing resolution. Low 390 mW power reduces patient-applied thermal load, and 1.8 V AVDD/DVDD simplifies battery-powered cart designs.
おすすめ
Portable Test Instrumentation
The LTC2183CUP fits portable oscilloscopes and spectrum analyzers requiring two matched 80 Msps channels with high SFDR. Its low power budget suits handheld battery-powered instruments where thermal management is constrained. Differential 2 Vp-p inputs accommodate standard probe attenuation networks. SPI programming allows mode switching between full-power 390 mW and lower-speed low-power operation, extending battery life when high sample rate is not required. The parallel CMOS output mode simplifies interfacing to low-cost FPGAs.
おすすめ
Non-Destructive Testing Ultrasound
The LTC2183CUP's dual simultaneous-sampling architecture digitizes transmit-burst and receive-echo paths or paired transducer signals in industrial flaw detectors. The 76.8 dB SNR detects small crack-reflected echoes in metals and composites. With 0.07 psRMS jitter the ADC preserves timing-of-flight accuracy needed for thickness gauging. Selectable CMOS or LVDS outputs interface to FPGA-based phased-array processing. The exposed-pad QFN-64 package provides low thermal resistance for continuous high-duty-cycle industrial scanning.
おすすめ
Software Defined Radio / I/Q Demodulation
The LTC2183CUP digitizes I and Q baseband signals from an analog quadrature demodulator directly into the FPGA. Simultaneous sampling eliminates I/Q phase mismatch that would corrupt image rejection. With 76.8 dB SNR and 90 dB SFDR the ADC supports wideband SDR applications including ham radio transceivers, software-defined cellular basebands, and signal-intelligence receivers. The LVDS output mode minimizes radiated emissions in dense RF-sensitive enclosures.
おすすめ
Radar and Lidar Signal Acquisition
The LTC2183CUP's dual 80 Msps channels simultaneously digitize in-phase and quadrature echoes for FMCW or chirp radar/lidar processing. The 90 dB SFDR preserves small returns near large nearby reflectors. Low 0.07 psRMS jitter enables precise round-trip-time measurement. Differential inputs reject common-mode interference from high-current laser diodes or RF transmitters. The 1.8 V supply simplifies integration with low-power FPGA SoCs used in compact automotive or surveillance lidar modules.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2183CUP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2185CUP | LTC2184CUP | LTC2180CUP | LTC2145CUP-12 | LTC2155CUP-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (UP) 9x9 mm | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) - same family | 64-QFN (UP) - same family |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit | 14 bit |
| Sample Rate | 80 Msps | 125 Msps | 105 Msps | 105 Msps | 25/40 Msps | 170 Msps |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Output Interface | CMOS / LVDS / DDR LVDS | CMOS / LVDS / DDR LVDS | CMOS / LVDS / DDR LVDS | CMOS / LVDS / DDR LVDS | CMOS / LVDS | CMOS / LVDS |
主な差別化要因
- Higher sample rate option in same package （vs LTC2185CUP)
- Lower-power variant with higher speed （vs LTC2184CUP)
- Same family higher-resolution alternative （vs LTC2155CUP-12)
- Dual simultaneous-sampling channels （vs LTC2175IUKG-14)
設計ノート
Estimated: route the analog inputs (INA+/INA-, INB+/INB-) as 100 ohm differential microstrip with matched length, and place the differential driver op-amp within 5mm of the ADC. The exposed thermal pad must be soldered to a continuous ground pour on inner layers, stitched with at least 9 thermal vias (0.3 mm drill) for heat dissipation. Place 0.1 uF X7R decoupling capacitors within 2 mm of each AVDD and DVDD pin, plus a single 10 uF bulk capacitor near the package.
The LTC2183CUP expects a high-quality differential encode clock (ENC+/ENC-) with low jitter. Source the clock from a low-noise PLL or a dedicated clock generator (e.g., LTC6951) rather than an FPGA output. Apply a clock duty-cycle stabilizer per datasheet recommendation. Maintain 50 ohm termination at the ADC clock pins if driven single-ended, or use a balun for differential drive.
Estimated: total 1.8 V supply current is approximately 215 mA (390 mW / 1.8 V), so use a low-noise LDO (e.g., LT3042) for AVDD rather than a switching regulator. Separate AVDD and DVDD domains with ferrite beads to prevent digital noise coupling into the reference. Keep analog ground and digital ground connected only at a single point near the exposed pad to avoid ground loops.
Do not skip the internal dither - for low-level inputs below -20 dBFS the LTC2183CUP's SFDR improves by 5-10 dB with dither enabled. Do not exceed 2 Vp-p differential input range or the input ESD diodes will clamp. Do not float the MODE pin - it must be tied HIGH for LVDS or LOW for CMOS. Use the SPI port to verify configuration after power-up.
コンプライアンス情報
RoHS and REACH compliant per Analog Devices product page. The #PBF suffix indicates lead-free finish. Not AEC-Q100 qualified - this is a C-grade (0C to +70C) commercial/industrial part, not automotive grade.
