LTC2205IUK - 16-Bit 65Msps ADC, 48-QFN | Analog Devices
部品番号: LTC2205IUK ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $92.5 | $92.50 |
| 10 | $85.2 | $852.00 |
| 100 | $78.1 | $7,810.00 |
| 500 | $74 | $37,000.00 |
| 1,000 | $70.56 | $70,560.00 |
LTC2205IUK 概要
An ADC (analog-to-digital converter) is a data-acquisition IC that samples a continuous analog waveform and produces a discrete digital code. Within the converter hierarchy it is a pipelined successive-approximation hybrid, which sits between flash converters (fastest, lowest resolution) and sigma-delta converters (highest resolution, slower). Pipelined ADCs like the LTC2205 strike a balance of 12-16 bit resolution at tens to hundreds of megasamples per second, making them standard for IF sampling, radar, test equipment, and software-defined radio.
Key features of the LTC2205IUK include 90 fsRMS ultralow aperture jitter for accurate undersampling of high-IF signals, ±4 LSB INL and ±1 LSB DNL (no missing codes) for excellent DC linearity, and a single 3.3V supply operation. Differential PECL/LVDS-compatible clock inputs and CMOS-compatible outputs simplify interface to FPGAs and DSPs. The -IUK industrial temperature grade is rated from -40C to +85C.
Architecturally, the device uses a multi-stage pipelined core with a proprietary front-end PGA and on-chip reference. Digital error correction across pipeline stages guarantees no missing codes at the full 65Msps rate, while internal calibration trims INL and DNL at production test. A separate analog and digital supply pin pair (AVDD/DVDD) is provided to allow clean power-rail isolation.
Typical applications include cellular base-station IF sampling, cable-headend QAM/QPSK demodulators, medical ultrasound beamformers, radar and electronic-warfare receivers, and high-end test and measurement digitizers. The wide 700 MHz input bandwidth also makes it well-suited for direct-IF software-defined radio designs.
When designing with the LTC2205IUK, place the analog input network (transformer or driver amp plus anti-alias filter) as close to the AIN pins as possible and keep AVDD/DVDD supplies well decoupled. The 48-QFN exposed pad must be soldered to a continuous ground plane to meet the 79 dB SNR spec, and a balanced differential clock source is essential to realize the 90 fs jitter figure.
This page synthesizes the 1ku list price, drop-in LTC2205/LTC2204/LTC2206 family alternatives, and practical PCB layout guidance that go beyond what is in the ADI datasheet alone.
ドロップイン代替品: LTC2205IUK — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2205IUK （同一形状・フットプリント） — 相違点: Aperture Jitter, Package, RoHS Status, Resolution, SFDR.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2204IUK#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2205IUK-14#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2205CUK#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2205IUK#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2207CUK#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2202IUK
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2205IUK 最大定格＆電気的特性
| 分解能 | 16 bit |
| Sample Rate | 65 Msps |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Bandwidth | 700 MHz |
| SNR | 79 dB |
| SFDR | 100 dB |
| Aperture Jitter | 90 fs RMS |
| INL (Max) | ±4 LSB |
| DNL (Max) | ±1 LSB (no missing codes) |
| Input Type | Differential, with PGA front end |
| 電源電圧 | 3.3 V (single) |
| Digital Output | CMOS-compatible |
| Clock Input | Differential PECL/LVDS-compatible |
| Operating Temperature (IUK grade) | -40C to +85C (industrial) |
| パッケージ | 48-lead QFN (7x7 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (#PBF suffix) |
| 1ku List Price (starting) | $70.56 (as of 2026-10-13, per ADI product page) |
LTC2205IUK ピン構成
| ピン 1 | AIN+ — Differential analog input, positive |
| ピン 2 | AIN- — Differential analog input, negative |
| ピン 3 | VCM — Common-mode voltage output for input coupling |
| ピン 4 | SENSE — Input range select / reference configuration |
| ピン 5 | VREF — Reference voltage bypass |
| ピン 6 | GND — Ground |
| ピン 7 | AVDD — 3.3V analog supply |
| ピン 8 | GND — Ground |
| ピン 9 | AVDD — 3.3V analog supply |
| ピン 10 | GND — Ground |
| ピン 11 | AVDD — 3.3V analog supply |
| ピン 12 | GND — Ground |
| ピン 13 | CLK+ — Differential sample clock, positive |
| ピン 14 | CLK- — Differential sample clock, negative |
| ピン 15 | GND — Ground |
| ピン 16 | OF — Output overflow flag |
| ピン 17 | DVDD — 3.3V digital supply |
| ピン 18 | GND — Ground |
| ピン 19 | D15 — CMOS data output, MSB |
| ピン 20 | D14 — CMOS data output |
| ピン 21 | D13 — CMOS data output |
| ピン 22 | D12 — CMOS data output |
| ピン 23 | D11 — CMOS data output |
| ピン 24 | D10 — CMOS data output |
| ピン 25 | D9 — CMOS data output |
| ピン 26 | D8 — CMOS data output |
| ピン 27 | DVDD — 3.3V digital supply |
| ピン 28 | GND — Ground |
| ピン 29 | D7 — CMOS data output |
| ピン 30 | D6 — CMOS data output |
| ピン 31 | D5 — CMOS data output |
| ピン 32 | D4 — CMOS data output |
| ピン 33 | D3 — CMOS data output |
| ピン 34 | D2 — CMOS data output |
| ピン 35 | D1 — CMOS data output |
| ピン 36 | D0 — CMOS data output, LSB |
| ピン 37 | GND — Ground |
| ピン 38 | DVDD — 3.3V digital supply |
| ピン 39 | GND — Ground |
| ピン 40 | MODE — Output mode / format select |
| ピン 41 | DITH — Dither enable |
| ピン 42 | SHDN — Shutdown (active high) |
| ピン 43 | NC — Not connected (per datasheet) |
| ピン 44 | AVDD — 3.3V analog supply |
| ピン 45 | GND — Ground |
| ピン 46 | PGA+ — PGA front-end positive output / test |
| ピン 47 | PGA- — PGA front-end negative output / test |
| ピン 48 | VBIAS — Bias voltage bypass |
主な用途
LTC2205IUK の用途: 6 件s: Cellular Base-Station IF Sampling, Cable-Headend QAM/QPSK Demodulator, Software-Defined Radio Direct-IF Digitizer, Medical Ultrasound Beamformer Receiver, Radar and Electronic-Warfare Receiver, High-End Test and Measurement Digitizer.
Cellular Base-Station IF Sampling
The LTC2205IUK fits cellular base-station IF sampling because its 700 MHz input bandwidth and 90 fs RMS aperture jitter allow accurate undersampling of intermediate frequencies well above the 65 Msps Nyquist limit, eliminating a downconversion stage. The 79 dB SNR and 100 dB SFDR preserve the carrier-to-noise ratio required for WCDMA, LTE, and multi-carrier GSM receivers. Placed after the analog AGC and anti-alias filter, the converter feeds digital data directly into an FPGA or DSP baseband processor. Engineers value this part here because its 3.3V single-supply operation simplifies base-station power architecture, while the 48-QFN exposed pad aids thermal dissipation in fanless outdoor units.
おすすめ
Cable-Headend QAM/QPSK Demodulator
The LTC2205IUK is well matched to cable-headend QAM/QPSK demodulation where 50-100 MHz IF blocks must be digitized at high spurious-free dynamic range to support 256-QAM and 1024-QAM constellations. The 100 dB SFDR guarantees that intermodulation spurs stay well below the dense symbol error floor, while the 16-bit resolution preserves enough ENOB for cable-DOCSIS downstream channels. Used in a double-conversion tuner or direct-IF digital tuner, the ADC outputs to a QAM demodulator block inside an FPGA. Designers choose this converter over a slower successive-approximation ADC because the pipelined sample rate keeps up with symbol throughput of multi-channel QAM aggregations.
おすすめ
Software-Defined Radio Direct-IF Digitizer
Software-defined radio designs benefit from the LTC2205IUK's combination of 16-bit resolution and 700 MHz input bandwidth, which permits direct sampling of HF/VHF first-IF signals without a second mixer stage. The 90 fs RMS aperture jitter preserves the modulation error rate of OFDM and QPSK waveforms, and the 79 dB SNR supports wide dynamic-range signals common in military and amateur SDR platforms. The 48-QFN footprint pairs naturally with FPGA-based DSP engines that perform channelization, demodulation, and decoding in real time. Compared with a 14-bit converter, the LTC2205IUK adds 2-3 dB of dynamic range, which directly translates to higher-order modulation capability in a given bandwidth.
おすすめ
Medical Ultrasound Beamformer Receiver
The LTC2205IUK supports medical ultrasound beamformer receivers where each channel of an 8-, 16-, or 32-element transducer array requires a high-resolution ADC running at tens of megasamples per second. Its 79 dB SNR preserves the dynamic range of reflected echo signals, while the pipelined architecture keeps per-channel power low enough to enable dense array integration. Placed after the LNA and TGC amplifier on each receive channel, the converter feeds beamforming delay-and-sum logic in an FPGA. Engineers choose the 48-QFN industrial-grade part because the -40C to +85C rating covers continuous-operation ultrasound carts without thermal derating.
おすすめ
Radar and Electronic-Warfare Receiver
Radar and electronic-warfare receivers use the LTC2205IUK to digitize wideband IF signals from microwave downconverters, where the 700 MHz input bandwidth and 90 fs jitter are essential for accurate pulse-shape reconstruction and PDW (pulse descriptor word) generation. The 100 dB SFDR ensures that small targets are not masked by intermodulation spurs of large co-channel signals. The 48-QFN package is small enough for high-channel-count EW receivers, and the 3.3V single-supply simplifies the ruggedized power tree. Compared to a 12-bit converter, the LTC2205IUK provides 16 dB more spurious-free dynamic range, materially improving detection probability for low-RCS targets.
おすすめ
High-End Test and Measurement Digitizer
The LTC2205IUK is a strong fit for high-end test and measurement digitizers such as oscilloscope input channels, spectrum-analyzer IF strips, and protocol analyzers, where 16-bit vertical resolution and 65 Msps real-time sample rate deliver a true 80 MHz capture bandwidth. The 79 dB SNR provides 13+ ENOB for accurate FFT-based spectral measurements, and the 90 fs jitter preserves phase-noise measurements on high-Q signals. The 48-QFN package drops directly onto existing digitizer daughter cards, and the parallel CMOS output simplifies capture-memory interfacing without an extra deserializer. This part is preferred here over a 14-bit alternative because the additional 2 bits translate directly to wider dynamic range in the same instrument form factor.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2205IUK — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2204IUK#PBF | LTC2205IUK-14#PBF | LTC2205CUK#PBF | LTC2207CUK#PBF |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7 mm) | 48-QFN (7x7 mm) - same | 48-QFN (7x7 mm) - same | 48-QFN (7x7 mm) - same | 48-QFN (7x7 mm) - same |
| Resolution | 16 bit | 16 bit | 14 bit | 16 bit | 16 bit |
| Sample Rate | 65 Msps | 40 Msps | 65 Msps | 65 Msps | 105 Msps |
| Input Bandwidth | 700 MHz | 700 MHz | 700 MHz | 700 MHz | 700 MHz |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +70C | Commercial 0C to +70C |
主な差別化要因
- Same 65 Msps / 16-bit / 700 MHz BW at the lower commercial price （vs LTC2205CUK#PBF)
- 16-bit resolution at the same pinout and speed as the 14-bit alternative （vs LTC2205IUK-14#PBF)
- Pin-compatible upgrade path to 105 Msps without PCB rework （vs LTC2207CUK#PBF)
設計ノート
The 48-QFN exposed pad MUST be soldered to a continuous, unbroken ground plane on the top layer for thermal dissipation and electrical grounding. Use an array of thermal vias (typically 9-16 vias on 0.5 mm pitch) under the EP to drop the ground connection to inner layers. This single layout decision is the difference between reaching the datasheet 79 dB SNR and losing 5-10 dB to ground bounce.
AVDD and DVDD must be powered from the same 3.3V rail but with a ferrite bead between them to isolate analog and digital return currents, per the LTC2205/LTC2204 datasheet (22054fc). Place a 10 uF bulk plus 0.1 uF and 10 nF ceramic decoupling capacitor as close as possible to every AVDD/DVDD pin pair. Star-ground the analog and digital grounds at the exposed pad. Estimated: a 50 mA analog load plus 30 mA digital load gives ~80 mA total at 3.3V = 0.26 W, well within the 48-QFN thermal envelope.
The CLK+ and CLK- inputs are differential PECL/LVDS-compatible; drive them from a low-phase-noise clock source such as the AD9516 or AD9548, with a 100 ohm differential termination placed as close to the pins as possible. A noisy clock is the dominant source of aperture-jitter degradation; 90 fs RMS jitter is only achievable when the clock is clean. Estimated: every 1 ps of clock jitter adds 1 LSB of noise at 65 Msps, so a 5 ps noisy clock could erase the 16-bit SNR advantage.
Do not route the CMOS D0-D15 output bus across a noisy digital region without ground shielding; the parallel outputs toggle at 65 MHz and couple noise back into AVDD if not properly isolated. Source-terminate the D0-D15 lines with 33-50 ohm series resistors at the LTC2205IUK end if the trace length to the FPGA exceeds ~25 mm. Also, the AIN+/AIN- analog inputs require a DC bias to the VCM pin voltage (mid-supply) - leaving them floating will not work and the converter will saturate immediately.
コンプライアンス情報
RoHS and lead-free compliance per the #PBF suffix (Analog Devices Pb-free designation). Industrial temperature grade -40C to +85C; not AEC-Q100 qualified - this is a commercial/industrial ADC, not automotive grade.
