LTC2216CUP - 16-Bit 80Msps Low Noise ADC | Analog Devices
部品番号: LTC2216CUP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $94.37 | $94.37 |
| 10 | $84.93 | $849.30 |
| 100 | $75.5 | $7,550.00 |
| 500 | $66.06 | $33,030.00 |
| 1,000 | $56.62 | $56,620.00 |
LTC2216CUP 概要
What is an ADC? An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes. Within the converter taxonomy, the LTC2216CUP belongs to the SAR/pipelined converter family (pipelined here) -> data converters -> mixed-signal ICs -> signal chain semiconductors. High-speed 16-bit converters sit at the boundary between precision measurement and communications infrastructure, where both dynamic range and sample rate determine system viability.
Key specifications include 80 Msps guaranteed sampling rate, 76 dBFS signal-to-noise ratio and 90 dB spurious-free dynamic range. The input stage accepts differential signals with 2.75 Vp-p full-scale, and the digital outputs are CMOS/LVDS compatible, providing flexible interfacing with FPGAs and DSPs. Internal references and a duty-cycle stabilizer reduce external component count and ease PCB layout.
The pipelined architecture distributes conversion across multiple low-resolution stages, combining high throughput with low power consumption (approximately 425 mW). The device integrates a high-bandwidth track-and-hold, internal reference, and programmable digital output timing, which minimizes downstream complexity while supporting demanding multi-carrier and broadband systems.
Typical applications include cellular base-station receivers, cable infrastructure head-ends, medical imaging front-ends, spectrum and signal analyzers, defense radar signal chains, and high-end test-and-measurement instrumentation. The combination of 16-bit resolution and 80 Msps throughput enables the digitization of intermediate-frequency (IF) signals in software-defined radio systems.
For design success, place the device on a multi-layer PCB with a solid ground plane and keep analog/digital sections physically separated. Use an ultra-low-jitter clock source at the encode input; encode jitter of even a few picoseconds directly degrades SNR. Properly terminate the differential analog inputs with a transformer or driver for best harmonic performance.
This page synthesizes distributor pricing, drop-in alternatives from the same ADC family, and practical design considerations not found in the manufacturer datasheet alone.
ドロップイン代替品: LTC2216CUP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2216CUP （同一形状・フットプリント） — 相違点: Package, Number of Channels, Input Range, Operating Temperature Range, SFDR.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2215CUP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2217CUP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2216CUP#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2216IUP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$37.8 / 個
データシートを見る →LTC2180CUP
✅ ドロップイン✓ 在庫あり
$41.72 / 個
データシートを見る →LTC2155CUP-12
✅ ドロップイン✓ 在庫あり
$44.25 / 個
データシートを見る →LTC2216CUP 最大定格＆電気的特性
| Manufacturer | Analog Devices |
| Part Number | LTC2216CUP |
| 分解能 | 16 bits |
| サンプリングレート | 80 Msps |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Range | 2.75 Vp-p |
| Input Frequency (max) | 400 MHz |
| Input Type | Differential |
| Analog Supply Voltage | 3.3 V |
| SNR | 78.5 dBFS at Nyquist |
| SFDR | 90 dB at Nyquist |
| Power Consumption | 425 mW (typical) |
| Digital Output | CMOS / LVDS compatible |
| パッケージ | 64-QFN (9x9 mm), HVQCCN |
| Temperature Grade | Commercial |
| RoHS | Compliant (PBF variants) |
LTC2216CUP ピン構成
| ピン 1 | OGND — Output driver ground |
| ピン 2 | DNC — Do not connect |
| ピン 3 | DNC — Do not connect |
| ピン 4 | VDD — Analog 3.3V supply |
| ピン 5 | D0 — Data output bit 0 (LSB) |
| ピン 6 | D1 — Data output bit 1 |
| ピン 7 | D2 — Data output bit 2 |
| ピン 8 | D3 — Data output bit 3 |
| ピン 9 | D4 — Data output bit 4 |
| ピン 10 | D5 — Data output bit 5 |
| ピン 11 | D6 — Data output bit 6 |
| ピン 12 | D7 — Data output bit 7 |
| ピン 13 | DGND — Digital ground |
| ピン 14 | D8 — Data output bit 8 |
| ピン 15 | D9 — Data output bit 9 |
| ピン 16 | D10 — Data output bit 10 |
| ピン 17 | D11 — Data output bit 11 |
| ピン 18 | D12 — Data output bit 12 |
| ピン 19 | D13 — Data output bit 13 |
| ピン 20 | D14 — Data output bit 14 |
| ピン 21 | D15 — Data output bit 15 (MSB) |
| ピン 22 | DGND — Digital ground |
| ピン 23 | VDD — Output driver 3.3V supply |
| ピン 24 | CLKOUT — Clock output (for output data alignment) |
| ピン 25 | OGND — Output driver ground |
| ピン 26 | DNC — Do not connect |
| ピン 27 | SENSE — Reference mode select (internal/external) |
| ピン 28 | VREF — Reference decoupling / external reference |
| ピン 29 | VREF — Reference decoupling |
| ピン 30 | REFBUF — Internal reference buffer output |
| ピン 31 | REFT — Reference top (bypass) |
| ピン 32 | REFB — Reference bottom (bypass) |
| ピン 33 | MODE — Output mode / format select |
| ピン 34 | OF — Output overflow flag |
| ピン 35 | OTR — Out-of-range indicator |
| ピン 36 | VCM — Common-mode output (1.475 V) |
| ピン 37 | VEE — Negative supply (grounded) |
| ピン 38 | AIN+ — Differential analog input (positive) |
| ピン 39 | AIN- — Differential analog input (negative) |
| ピン 40 | VEE — Negative supply (grounded) |
| ピン 41 | VEE — Negative supply (grounded) |
| ピン 42 | VEE — Negative supply (grounded) |
| ピン 43 | VDD — Analog 3.3V supply |
| ピン 44 | VEE — Negative supply (grounded) |
| ピン 45 | VDD — Analog 3.3V supply |
| ピン 46 | GND — Analog ground |
| ピン 47 | VDD — Analog 3.3V supply |
| ピン 48 | GND — Analog ground |
| ピン 49 | CLK+ — Differential encode clock (positive) |
| ピン 50 | CLK- — Differential encode clock (negative) |
| ピン 51 | GND — Analog ground |
| ピン 52 | DCS — Duty-cycle stabiliser enable |
| ピン 53 | DGS — Digital gain select |
| ピン 54 | SHIFT — Data output shift clock enable |
| ピン 55 | PD — Power-down input |
| ピン 56 | DGS — Digital gain select |
| ピン 57 | VEE — Negative supply (grounded) |
| ピン 58 | VEE — Negative supply (grounded) |
| ピン 59 | VEE — Negative supply (grounded) |
| ピン 60 | VEE — Negative supply (grounded) |
| ピン 61 | VEE — Negative supply (grounded) |
| ピン 62 | VEE — Negative supply (grounded) |
| ピン 63 | VEE — Negative supply (grounded) |
| ピン 64 | VEE — Negative supply (grounded) |
| ピン EP | EP — Exposed pad - solder to PCB ground plane (must be connected) |
主な用途
LTC2216CUP の用途: 7 件s: Cellular Base-Station Receiver IF Sampling, Software-Defined Radio and Broadband Receiver, Medical Imaging Ultrasound Receiver, Spectrum and Signal Analyser Digitiser, Defense and Radar Signal-Processing Front-End, Test-and-Measurement Digitiser and ATE, Cable Infrastructure Head-End and CMTS IF Sampling.
Cellular Base-Station Receiver IF Sampling
The LTC2216CUP digitises intermediate-frequency signals in 3G/4G/5G receiver chains at the 80 Msps Nyquist boundary, providing 78.5 dBFS SNR and 90 dB SFDR needed to resolve multicarrier symbols. With a fixed 2.75 Vp-p differential input and 400 MHz input bandwidth, it connects directly to a front-end SAW filter and transformer driver. The 64-QFN (9x9 mm) package and ~425 mW power fit dense remote-radio-head cards where thermals are constrained. Using a sub-picosecond encode clock preserves the full SNR envelope.
おすすめ
Software-Defined Radio and Broadband Receiver
In software-defined radios, the LTC2216CUP captures signal-bandwidths up to ~38 MHz at 80 Msps, allowing digital demodulation in FPGA fabric. Its 16-bit dynamic range resolves both strong and weak simultaneous signals, while the 90 dB SFDR limits intermodulation spurs that would otherwise desensitise the receiver. The 64-QFN package occupies only 81 mm² on the PCB, enabling multiboard stacked SDR architectures. Combined with a precision clock source, the LTC2216CUP delivers laboratory-class DC-to-100 MHz signal capture.
おすすめ
Medical Imaging Ultrasound Receiver
Ultrasound front-ends use the LTC2216CUP to digitise time-gain-controlled echo signals at 80 Msps with 16-bit resolution, capturing the full harmonic content of returned ultrasound pulses. The 78.5 dBFS SNR preserves dynamic range required for tissue harmonic imaging, while the 64-QFN footprint and 425 mW power simplify per-channel board density. Multiple LTC2216CUP devices can be synchronised to a common encode clock for parallel beamformer tiles. Differential analog inputs reject common-mode noise from the transmit/receive switch.
おすすめ
Spectrum and Signal Analyser Digitiser
Wide-bandwidth spectrum analysers employ the LTC2216CUP as the final IF digitiser, where 80 Msps sampling captures the analysis bandwidth with FFT processing in the host. The 90 dB SFDR ensures spurs stay well below the analyser noise floor, while the 78.5 dBFS SNR supports deeper integration. The 64-QFN package enables compact portable analyser designs. Pair the converter with a low-noise clock source to achieve the published SNR across the full input bandwidth.
おすすめ
Defense and Radar Signal-Processing Front-End
Radar and electronic-warfare receivers need wide instantaneous bandwidth and high dynamic range. The LTC2216CUP delivers 78.5 dBFS SNR / 90 dB SFDR at 80 Msps with 400 MHz input bandwidth, allowing direct digitisation of IF outputs from radar mixers. The 64-QFN (9x9 mm) package and solid ground/thermal pad suit ruggedised MIL-boards where thermal cycling and shock-resistance are required. Designers select the industrial-temperature LTC2216IUP variant for harsh-environment upgrade.
おすすめ
Test-and-Measurement Digitiser and ATE
Automated-test-equipment (ATE) digitiser cards use the LTC2216CUP to sample analog waveforms at 80 Msps with 16-bit integrity, enabling deep-memory captures of complex stimulus-response profiles. The fixed 2.75 Vp-p input range, low differential nonlinearity, and configurable CMOS/LVDS outputs reduce external IC count. The 64-QFN (9x9 mm) package supports PXI-style PXIe card form factors. Combine the converter with FPGA post-processing for real-time protocol analysers and waveform recorders.
おすすめ
Cable Infrastructure Head-End and CMTS IF Sampling
In DOCSIS 3.1 cable head-ends, the LTC2216CUP serves as the IF digitiser after the upstream/downstream conversion stage. Its 80 Msps rate with 78.5 dBFS SNR preserves the wide channel-bonded downstream carriers, and the 90 dB SFDR limits spurious artefacts in dense OFDM bands. The 64-QFN footprint supports high-density multi-channel head-end cards where each demodulator requires its own ADC. The internal voltage reference and duty-cycle stabiliser simplify calibration headroom.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2216CUP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2215CUP | LTC2217CUP | LTC2216CUP#PBF | LTC2216IUP | LTC2180CUP | LTC2155CUP-12 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Resolution (bits) | 16 | 16 | 16 | 16 | 16 | 16 | 12 |
| Sample Rate (Msps) | 80 | 65 | 105 | 80 | 80 | 105 | 170 |
| Input Range (Vp-p) | 2.75 | 2.75 | 2.75 | 2.75 | 2.75 | 2.75 | 2.0 |
| SNR (dBFS at Nyquist) | 78.5 | 77 | 78 | 78.5 | 78.5 | 77 | 70 |
| Power (mW, typ) | 425 | 380 | 475 | 425 | 425 | 500 | 550 |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Industrial | Commercial | Commercial |
| Pin-to-Pin Drop-In | - | Yes | Yes | Yes | Yes | Yes | Yes |
主な差別化要因
- True 80 Msps throughput in a compact 64-QFN (9x9 mm) - small area than BGA alternatives （vs LTC2287 (64-QFN with 80 Msps but lower SNR))
- Upward and downward speed scalability within the same 64-QFN pinout （vs LTC2155CUP-12)
- Commercial-grade temperature compliance matches the broad SLB commercial band （vs LTC2216IUP (industrial-grade))
設計ノート
Use a 4-layer or 6-layer PCB with dedicated ground and power planes. Place all analog bypass capacitors (10 uF tantalum or ceramic + 0.1 uF ceramic) within 5 mm of each analog VDD pin. The 64-QFN exposed pad must be soldered to a continuous ground-plane island with at least 8 thermal vias to inner ground layers for 0.5 W dissipation at 425 mW operation.
Route differential analog inputs (AIN+, AIN-) and differential encode clock (CLK+, CLK-) with matched 100-ohm differential microstrip on the top layer over an unbroken ground reference. Trace-length matching to within 0.5 mm (about 25 ps at 5 ps/mm) preserves best SNR at high input frequencies. Keep digital outputs well separated from analog inputs to avoid digital-noise coupling.
Encode-clock jitter above 200 fs RMS directly degrades SNR by 4-5 dB; use a low-jitter clock generator such as AD9516-4 with sub-150 fs integrated jitter. Do not float the SENSE, DCS, MODE, or DGS pins - tie them high or low per datasheet Table 2. The exposed pad pin MUST be soldered; failing to do so reduces max junction temperature capability and worsens thermal stress on adjacent analog inputs.
Drive the analog inputs through a broadband transformer (e.g., ADT1-1WT) or an active differential driver (AD8138, ADA4940) to preserve the 2.75 Vp-p full-scale input with proper 50-ohm termination. Terminate the encode clock with a 200-ohm differential across CLK+ and CLK- near the IC. Add a 100-ohm series ferrite bead on each VDD rail for clean dc and low-noise analog supply.
コンプライアンス情報
RoHS compliance applies to #PBF tape-and-reel variants; LTC2216CUP (UP) ordering code is also lead-free per Analog Devices product-page declaration.
