LTC2228IUH - 12-Bit 65Msps 3V ADC, 32-QFN | Analog Devices
部品番号: LTC2228IUH ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $17.5 | $17.50 |
| 10 | $15.75 | $157.50 |
| 100 | $14 | $1,400.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.85 | $10,850.00 |
LTC2228IUH 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog input and produces a discrete-time digital code proportional to the input voltage. Pipelined ADCs like the LTC2228 split the conversion into cascaded low-resolution stages with digital error correction, enabling high sample rates (>10 MHz) at moderate resolution (10-14 bits). They sit within the broader taxonomy of data-converter IC -> mixed-signal IC -> semiconductor device, and they are the interface between analog front-ends and digital signal processors, FPGAs, or ASICs.
Key features of the LTC2228IUH include 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, guaranteeing spectral purity for cellular baseband, IF sampling, and portable instrumentation applications. The device accepts a single-ended CLK input that controls converter operation and conversion start, simplifying board layout by removing the need for a complementary clock. A separate output supply pin (OVDD) lets the outputs swing between 0.5 V and 3.6 V, allowing direct connection to 1.8 V, 2.5 V, or 3.3 V logic families without level shifters.
Typical applications for the LTC2228IUH include cellular baseband transceiver IF sampling, ultrasound and medical imaging front-ends, portable and battery-powered test instrumentation, CCD imaging digitizers, and cable-head-end digital receivers. Its low 3 V power consumption makes it attractive for power-constrained designs, while the wide AC performance margin accommodates broadband signals up to the Nyquist band.
When designing with the LTC2228IUH, place the input network as close as possible to the analog input pin and provide a low-jitter clock source - the SNR budget at 65 Msps degrades by approximately 1 dB for every 1 ps of clock jitter. Decouple OVDD and AVDD separately with 0.1 µF ceramic capacitors near the pins, and tie the exposed pad to a clean analog ground plane for thermal and electrical performance.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not collated in the manufacturer datasheet, providing information gain beyond what distributor or manufacturer product pages offer.
ドロップイン代替品: LTC2228IUH — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2228IUH （同一形状・フットプリント） — 相違点: Sample Rate, Package, Resolution, RoHS Status, Missing Codes.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2227IUH
✅ ドロップイン✓ 在庫あり
$9.05 / 個
データシートを見る →LTC2228CUH#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2228IUH#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2245IUH
✅ ドロップイン✓ 在庫あり
$10.4 / 個
データシートを見る →AD9246
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2228IUH 最大定格＆電気的特性
| 分解能 | 12 bits |
| Sample Rate | 65 Msps |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Supply Voltage (Analog) | 3 V (typical), 2.7 V to 3.4 V range |
| Output Supply Voltage (OVDD) | 0.5 V to 3.6 V |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.15 LSB |
| Transition Noise | 0.25 LSB RMS |
| SNR at Nyquist | 71.3 dB |
| SFDR at Nyquist | 90 dB |
| Missing Codes | None over temperature |
| Clock Input | Single-ended |
| パッケージ | 32-pin QFN (5x5 mm) with exposed pad |
| Operating Temperature (Industrial -I grade) | -40 °C to +85 °C |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (PBF suffix denotes lead-free) |
LTC2228IUH ピン構成
| ピン 1 | OGND — Output driver ground |
| ピン 2 | D11 — Data output bit 11 (LSB) |
| ピン 3 | D10 — Data output bit 10 |
| ピン 4 | D9 — Data output bit 9 |
| ピン 5 | D8 — Data output bit 8 |
| ピン 6 | D7 — Data output bit 7 |
| ピン 7 | D6 — Data output bit 6 |
| ピン 8 | D5 — Data output bit 5 |
| ピン 9 | D4 — Data output bit 4 |
| ピン 10 | D3 — Data output bit 3 |
| ピン 11 | D2 — Data output bit 2 |
| ピン 12 | D1 — Data output bit 1 |
| ピン 13 | D0 — Data output bit 0 (MSB-related) |
| ピン 14 | OVDD — Output supply (0.5 V to 3.6 V) |
| ピン 15 | CLK — Single-ended clock input |
| ピン 16 | CLKOUT — Clock output (programmable) |
| ピン 17 | OGND — Output driver ground (alternate) |
| ピン 18 | CS — Chip select (active low) |
| ピン 19 | SHDN — Shutdown (active low) |
| ピン 20 | MODE — Output mode select |
| ピン 21 | AVDD — Analog supply 3 V |
| ピン 22 | REFH — Reference high decoupling |
| ピン 23 | REFL — Reference low decoupling |
| ピン 24 | VREF — Internal reference voltage |
| ピン 25 | AGND — Analog ground |
| ピン 26 | AIN+ — Analog input non-inverting |
| ピン 27 | AIN- — Analog input inverting |
| ピン 28 | NC — Not connected |
| ピン 29 | OF — Overflow output |
| ピン 30 | DNC — Do not connect |
| ピン 31 | NC — Not connected |
| ピン 32 | NC — Not connected |
主な用途
LTC2228IUH の用途: 7 件s: Cellular Baseband IF Sampling, Medical Ultrasound Imaging Front-End, Portable Battery-Powered Test Instrumentation, CCD Imaging Digitization, Cable Head-End Digital Receivers, Radar and Pulse-Processing Intermediate-Frequency Sampling, Software-Defined Radio (SDR) IF Sampling.
Cellular Baseband IF Sampling
The LTC2228IUH samples the intermediate-frequency (IF) output of cellular transceivers at up to 65 Msps with 71.3 dB SNR and 90 dB SFDR at the Nyquist frequency. Its single 3 V analog supply and separate 0.5 V to 3.6 V OVDD simplify power-tree design in 4G/5G modules, allowing direct connection to 1.8 V baseband ASICs without level shifters. The wide AC performance margin accommodates multi-carrier GSM, WCDMA, and LTE signals while meeting EVM and blocker requirements.
おすすめ
Medical Ultrasound Imaging Front-End
Portable ultrasound beamformers use the LTC2228IUH to digitize individual transducer channels at 65 Msps, capturing full-bandwidth acoustic echoes in real time. The 71.3 dB SNR preserves dynamic range for B-mode and Doppler imaging, while the 0.25 LSB RMS transition noise keeps low-amplitude reflections above the quantization noise floor. The 3 V supply enables battery-powered cart designs where heat dissipation and runtime matter, and the 32-QFN (5x5) package fits channel-density layouts of 64- and 128-channel probes.
おすすめ
Portable Battery-Powered Test Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules use the LTC2228IUH to capture wideband analog signals at 65 Msps on a single 3 V rail. The pipelined architecture produces one conversion per clock cycle, minimizing latency for trigger-to-capture response times. With ±0.3 LSB INL and ±0.15 LSB DNL, vertical accuracy is preserved without recalibration, and the separate OVDD domain matches modern 1.8 V FPGAs and microcontrollers in the same enclosure.
おすすめ
CCD Imaging Digitization
Scientific and machine-vision cameras route CCD outputs through the LTC2228IUH, exploiting its 71.3 dB SNR to preserve photon-limited signal-to-noise ratio per pixel. The 65 Msps rate comfortably digitizes progressive-scan video at full resolution without temporal aliasing, and the 0.5 V to 3.6 V output supply connects directly to modern image-processor ASICs. The pin-compatible LTC2227IUH (40 Msps) is sometimes preferred for cost-down 30 fps designs.
おすすめ
Cable Head-End Digital Receivers
DOCSIS and QAM receiver designs downconvert and digitize the downstream cable spectrum using the LTC2228IUH, where 71.3 dB SNR and 90 dB SFDR are essential for low bit-error rate (BER) at 64-QAM and 256-QAM constellations. The single-ended clock input eliminates the need for a complementary clock generator, simplifying PCB layout in dense multi-channel receiver cards. The 3 V analog supply keeps board-level power dissipation manageable for head-end chassis.
おすすめ
Radar and Pulse-Processing Intermediate-Frequency Sampling
Pulsed-radar IF strips digitize at 65 Msps using the LTC2228IUH to capture the pulse envelope for matched filtering and Doppler processing. The 71.3 dB SNR preserves target-detection margin, while the 0.25 LSB RMS transition noise floor reduces false alarms in clutter. The industrial -40 °C to +85 °C temperature rating (IUH grade) suits outdoor and avionics environments, and the 32-QFN (5x5) footprint enables dense multi-channel digitizer boards.
おすすめ
Software-Defined Radio (SDR) IF Sampling
Wideband SDR receivers use the LTC2228IUH to sample intermediate-frequency stages at 65 Msps, satisfying wide bandwidth requirements up to 30 MHz without requiring a separate analog demodulation stage. The pipelined architecture provides deterministic latency, simplifying alignment of multiple receiver chains in MIMO and direction-finding applications. The 3 V supply and 32-QFN (5x5) package fit SDR dongles and field-deployed radios where size, weight, and power dominate the BOM.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2228IUH — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2227IUH | LTC2228CUH#PBF | LTC2228IUH#PBF | LTC2245IUH | AD9246 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 32-QFN (5x5) | 32-QFN (5x5) - same | 32-QFN (5x5) - same | 32-QFN (5x5) - same | 32-QFN (5x5) - same | 32-QFN (5x5) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 14 bits | 12 bits |
| Sample Rate | 65 Msps | 40 Msps | 65 Msps | 65 Msps | 80 Msps | 65 Msps |
| Supply Voltage | 2.7 V to 3.4 V (3 V typical) | 2.7 V to 3.4 V | 2.7 V to 3.4 V | 2.7 V to 3.4 V | 2.7 V to 3.4 V | 2.7 V to 3.4 V |
| Operating Temperature | -40 °C to +85 °C (Industrial) | -40 °C to +85 °C | 0 °C to +70 °C (Commercial) | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
主な差別化要因
- Pin-compatible slower and faster variants within the same family （vs LTC2227IUH / LTC2228CUH#PBF / LTC2228IUH#PBF / LTC2245IUH)
- Historical AD9246 drop-in compatibility from the same vendor （vs AD9246)
- Separate OVDD enables direct connection to 1.8 V, 2.5 V, and 3.3 V logic （vs ADCs that share a single supply rail)
設計ノート
Route the single-ended CLK signal with controlled 50 Ω impedance and place it as far as possible from the analog input traces to prevent digital clock noise from coupling into the sampled input. ADI recommends a low-jitter clock source - jitter above 1 ps degrades SNR by approximately 1 dB per picosecond at 65 Msps with a 30 MHz input signal. Use a clock buffer/PLL filter network if the FPGA clock is not within the SNR budget.
Decouple AVDD and OVDD separately with 0.1 µF ceramic capacitors placed within 3 mm of their respective pins. Use a ferrite bead between the 3 V analog rail and the 1.8 V/2.5 V/3.3 V digital rail to isolate switching-noise feedback from the FPGA into the analog domain. The exposed pad (pin 33) must be soldered to a low-impedance analog ground plane; this serves both thermal (dissipates ~150 mW at full speed) and electrical (lowers ground bounce) functions.
Driving the analog input with a DC-coupled amplifier without an anti-alias filter will allow out-of-band interferers to alias into the baseband. Place a second-order or higher low-pass filter with bandwidth matched to your Nyquist rate at the AIN+ pin. Avoid routing digital outputs parallel to analog input traces - each D0-D11 transition injects ≈5 mV of coupling into adjacent analog traces for ~3 cm of parallel run, which is well above the 0.25 LSB RMS noise floor.
コンプライアンス情報
RoHS/REACH compliance confirmed by '#PBF' suffix per ADI ordering convention. Lead-free termination finish. AEC-Q100 not applicable - this is a commercial/industrial-grade ADC, not automotive qualified.