LTC2263IUJ-14 - 14-Bit 25Msps Dual ADC | Analog Devices
部品番号: LTC2263IUJ-14 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.5 | $10,250.00 |
| 1,000 | $18.25 | $18,250.00 |
LTC2263IUJ-14 概要
An ADC (analog-to-digital converter) is a mixed-signal semiconductor that samples continuous analog input voltages and produces discrete digital codes at a fixed sample rate; pipelined ADCs use a cascade of low-resolution stages to achieve high throughput at modest power, making them the workhorse architecture for communications, imaging, and instrumentation. The LTC2263IUJ-14 belongs to the power-management-and-conversion family and specifically to the pipelined ADC sub-class, integrating two simultaneously-sampling converters, internal reference, and LVDS drivers in one IC. Its 1.8 V single-supply operation simplifies power-tree design and pairs naturally with LVDS-capable FPGAs.
Key features of the LTC2263IUJ-14 include 73.4 dB SNR, 90 dB SFDR (typical), 25 Msps per-channel sample rate, serial LVDS output with 2-lane or 1-lane option, internal bandgap reference, low power dissipation (typical 60 mW per channel at 25 Msps), and an operating temperature range of -40°C to +85°C (I-grade). The exposed pad on the QFN-40 package provides a low thermal-resistance path (θJA of approximately 33°C/W), enabling compact multi-channel designs without external heatsinking.
Typical applications for the LTC2263IUJ-14 include high-speed data acquisition, communications receivers, digital oscilloscopes, medical imaging front-ends, multi-channel software-defined radio (SDR), and portable instrumentation. Its dual simultaneous-sampling architecture is especially suited to I/Q baseband, diversity receivers, and time-interleaved measurement systems where channel-to-channel phase coherence is critical.
When designing with this ADC, maintain a multilayer PCB with an unbroken internal ground plane beneath the device, drive each analog input differentially for best SFDR, and decouple the 1.8 V supply with 1 µF and 0.1 µF ceramics placed within a few millimetres of the supply pins. The exposed pad must be soldered to a low-impedance ground plane to achieve the rated thermal and electrical performance.
ドロップイン代替品: LTC2263IUJ-14 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2263IUJ-14 （同一形状・フットプリント） — 相違点: Package, Number of Channels, Resolution, RoHS Status, Sample Rate.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2263CUJ-14#PBF
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LTC2264IUJ-14#PBF
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LTC2265IUJ-14#PBF
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LTC2260IUJ-12#PBF
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LTC2262IUJ-12#PBF
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LTC2258IUJ-14#PBF
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LTC2263IUJ-14 最大定格＆電気的特性
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Part Number | LTC2263IUJ-14 |
| Description | 14-Bit, 25 Msps, Low Power Dual ADC |
| 分解能 | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 25 Msps per channel |
| Architecture | Pipelined |
| 電源電圧 | 1.8 V single supply |
| INL (Typical) | ±1 LSB |
| DNL (Typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| Missing Codes | None over temperature |
| Digital Output | Serial LVDS (2-lane or 1-lane mode) |
| Analog Input | Differential (recommended) |
| 動作温度範囲 | -40°C to +85°C (I-grade) |
| パッケージ | 40-QFN (6x6 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (#PBF suffix) |
LTC2263IUJ-14 ピン構成
| ピン 1 | AIN1+ — Channel 1 analog input, positive (differential) |
| ピン 2 | AIN1- — Channel 1 analog input, negative (differential) |
| ピン 3 | AVDD1 — 1.8V analog supply for channel 1 |
| ピン 4 | AVSS1 — Analog ground for channel 1 |
| ピン 5 | REF — Internal reference decoupling |
| ピン 6 | REFT — Reference top decoupling |
| ピン 7 | REFB — Reference bottom decoupling |
| ピン 8 | AVDD — Analog 1.8V supply |
| ピン 9 | AVSS — Analog ground |
| ピン 10 | OGND — Output driver ground |
| ピン 11 | OVDD — LVDS output driver 1.8V supply |
| ピン 12 | FRAME — Frame synchronization output |
| ピン 13 | DCO — DDR LVDS data clock output |
| ピン 14 | DAO+ — Channel 1 LVDS data output, positive |
| ピン 15 | DAO- — Channel 1 LVDS data output, negative |
| ピン 16 | DBO+ — Channel 2 LVDS data output, positive |
| ピン 17 | DBO- — Channel 2 LVDS data output, negative |
| ピン 18 | MODE — 1-lane / 2-lane mode select |
| ピン 19 | OF — Output format select |
| ピン 20 | CS — Chip select / SPI serial interface |
| ピン 21 | SCK — Serial interface clock |
| ピン 22 | SDO — Serial interface data output |
| ピン 23 | SDI — Serial interface data input |
| ピン 24 | OGND — Output driver ground |
| ピン 25 | CLK+ — Sample clock input, positive |
| ピン 26 | CLK- — Sample clock input, negative |
| ピン 27 | AVDD2 — Analog 1.8V supply for channel 2 |
| ピン 28 | AVSS2 — Analog ground for channel 2 |
| ピン 29 | AIN2- — Channel 2 analog input, negative |
| ピン 30 | AIN2+ — Channel 2 analog input, positive |
| ピン 31 | AVSS — Analog ground |
| ピン 32 | AVDD — Analog 1.8V supply |
| ピン 33 | NC — Not connected |
| ピン 34 | NC — Not connected |
| ピン 35 | NC — Not connected |
| ピン 36 | NC — Not connected |
| ピン 37 | NC — Not connected |
| ピン 38 | NC — Not connected |
| ピン 39 | NC — Not connected |
| ピン 40 | AVDD — Analog 1.8V supply |
主な用途
LTC2263IUJ-14 の用途: 6 件s: Multi-Channel Data Acquisition, Communications Receiver Baseband, Digital Oscilloscope Front-End, Medical Imaging Front-End, Software Defined Radio (SDR), Portable Test & Measurement.
Multi-Channel Data Acquisition
The LTC2263IUJ-14 is purpose-built for multi-channel data acquisition systems where two simultaneously-sampled signals must be digitized with channel-to-channel phase coherence. Its dual 25 Msps, 14-bit channels with ±1 LSB INL and 1.2 LSB RMS transition noise provide enough dynamic range for instrumentation-class front-ends. The serial LVDS output (2-lane or 1-lane mode) reduces FPGA pin count, and the 1.8 V single supply simplifies the power tree. Place the ADC close to the analog front-end, use a multilayer PCB with unbroken ground plane, and drive inputs differentially with a low-jitter clock to extract maximum SNR across the 12.5 MHz Nyquist band.
おすすめ
Communications Receiver Baseband
In digital communications receivers, the LTC2263IUJ-14 simultaneously digitizes the I and Q baseband outputs of a quadrature demodulator with phase-locked sampling. Its 73 dB SNR and 90 dB SFDR maintain EVM headroom for high-order QAM constellations, and the dual-channel sampling ensures I/Q timing skew is zero - critical for demodulation accuracy. The 25 Msps per channel comfortably covers wideband LTE, 5G NR sub-6 intermediate-frequency, and proprietary OFDM waveforms after baseband mixing. The 1.8 V operation also makes it natural to pair with modern baseband SoCs and FPGAs.
おすすめ
Digital Oscilloscope Front-End
The LTC2263IUJ-14 is a strong fit for two-channel digital-storage oscilloscope and digitizer front-ends requiring 14-bit amplitude resolution for high-fidelity waveform capture. Its 1.2 LSB RMS transition noise and ±0.3 LSB DNL support small-signal detail recovery in the presence of large dynamic-range inputs, and its dual channels enable simultaneous multi-probe acquisition. The serial LVDS output pairs directly with high-performance FPGAs that perform timebase triggering and deep-memory storage. Designers can scale to four channels by combining two LTC2263IUJ-14 ICs synchronized via a shared frame clock.
おすすめ
Medical Imaging Front-End
Ultrasound and other medical imaging front-ends require simultaneous multi-channel sampling of analog receive signals with high dynamic range and low noise. The LTC2263IUJ-14's two simultaneously-sampling 14-bit channels at 25 Msps, 1.2 LSB RMS noise, and 1.8 V operation support portable ultrasound probe electronics where power and channel density are constrained. Multiple devices can be time-interleaved for 8, 16, or 64-channel probe arrays, with each LTC2263 pair contributing one differential I/Q slice to the digital beamformer. Industrial temperature grade supports clinical and field-deployable imaging platforms.
おすすめ
Software Defined Radio (SDR)
Software-defined-radio platforms benefit from the LTC2263IUJ-14's dual simultaneous-sampling channels when capturing I/Q data streams from a quadrature demodulator or two antennas in a diversity configuration. Its 14-bit resolution and 73 dB SNR preserve the modulation fidelity needed for narrowband standards such as DVB, ISDB-T, and proprietary sub-GHz protocols, while the 1.8 V supply simplifies battery-powered portable SDR designs. The serial LVDS output reduces FPGA I/O pressure when multiple ADC pairs are aggregated, and exposed-pad QFN-40 packaging supports dense PCB layouts with good thermal dissipation.
おすすめ
Portable Test & Measurement
Portable and handheld test-and-measurement instruments - spectrum analyzers, RF probes, EMI receivers - require dense multi-channel digitization at low power. The LTC2263IUJ-14's 60 mW per channel dissipation and 1.8 V supply extend battery runtime while delivering 14-bit precision for amplitude-accurate measurements. Two channels fit into compact probes for differential voltage measurements or two-tone RF analysis. The exposed-pad QFN-40 package and industrial temperature range support field-deployed units that must operate in uncontrolled thermal environments while retaining full SNR and SFDR specifications.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2263IUJ-14 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2263CUJ-14#PBF | LTC2264IUJ-14#PBF | LTC2265IUJ-14#PBF | LTC2260IUJ-12#PBF | LTC2262IUJ-12#PBF |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit | 12 bit |
| Sample Rate | 25 Msps | 25 Msps | 40 Msps | 65 Msps | 105 Msps | 40 Msps |
| Number of Channels | 2 (simultaneous sampling) | 2 | 2 | 2 | 2 | 2 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Operating Temperature | -40°C to +85°C (I-grade) | 0°C to +70°C (C-grade) | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C |
主な差別化要因
- Dual simultaneous-sampling 14-bit channels at 25 Msps in a single 40-QFN (6x6) IC （vs LTC2258IUJ-14 (single-channel))
- 60 mW per channel power at 25 Msps (1.8 V single supply) （vs LTC2260IUJ-12 (12-bit 105 Msps cousin))
- Industry-standard serial LVDS output with 1-lane / 2-lane mode select （vs CMOS-parallel-output ADCs)
設計ノート
Use a multilayer PCB with an unbroken internal ground plane beneath the ADC for best noise performance. The QFN-40 exposed pad (pin 41) MUST be soldered to a low-impedance ground plane with multiple thermal vias to keep θJA near the 33°C/W rating. Decouple every AVDD pin with a 0.1 µF ceramic placed within 2-3 mm of the pin, plus a shared 10 µF bulk tantalum or polymer capacitor at the ADC supply node. Keep digital LVDS traces short and length-matched within the data-pair to maintain timing margins at 25 Msps.
Drive each analog input differentially (e.g., via a transformer or differential driver such as the LT6409) - single-ended drive significantly degrades SFDR and SNR. Provide a low-jitter, low-phase-noise differential clock to CLK+/CLK-; clock jitter of 1 ps RMS directly reduces SNR by approximately 2 dB at 12.5 MHz input. Do not exceed the absolute-maximum ratings of AVDD at 2.0 V or input common-mode outside the datasheet range, or the part will latch or suffer permanent damage. Ensure MODE, OF, and CS logic levels are stable at power-up.
Estimated total power dissipation at 25 Msps, both channels active, is approximately 120 mW with a 1.8 V supply. With QFN-40 θJA around 33°C/W, the junction temperature rise above ambient is approximately 4°C - well within the +85°C industrial limit. If both channels run at higher sample rates (via the LTC2264/LTC2265 drop-in upgrade), verify dissipation rises proportionally and re-confirm thermal margin. No external heatsink is required, but adequate airflow over the exposed pad region is recommended for sealed enclosures.
Place a 100 Ω differential termination resistor across each LVDS pair (DAO+/DAO-, DBO+/DBO-, DCO) as close to the FPGA receiver pins as possible to suppress reflections at 25 Msps DDR clock rates. Route CLK+/CLK- with controlled 100 Ω differential impedance and length-match within ±0.5 mm to the DCO/DAO/DBO lanes to avoid setup/hold violations. Keep ADC analog and digital ground regions separated until they meet at a single point under the exposed pad, or use a guard ring to isolate digital return currents from sensitive analog input pins.
コンプライアンス情報
RoHS/lead-free compliance confirmed by the #PBF suffix on the manufacturer part number; AEC-Q100 automotive qualification is not applicable for this industrial-grade ADC. REACH compliance per Analog Devices product declaration.