LTC2321HUFD-12 - Dual 12-Bit+Sign SAR ADC | Analog Devices
部品番号: LTC2321HUFD-12 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $9.15 | $9.15 |
| 10 | $8.42 | $84.20 |
| 100 | $7.18 | $718.00 |
| 500 | $6.31 | $3,155.00 |
| 1,000 | $5.62 | $5,620.00 |
LTC2321HUFD-12 概要
A successive approximation register (SAR) ADC is a converter architecture that resolves the analog input one bit per internal clock cycle using a binary search through a capacitive DAC network. SAR ADCs are valued for their deterministic latency, lack of pipeline delay, and excellent DC accuracy, sitting in the converter family alongside flash, pipeline, and sigma-delta ADCs as the preferred choice for multiplexed data acquisition, industrial control loops, and motor control where deterministic per-sample timing matters.
Key features of the LTC2321HUFD-12 include 2 Msps per channel simultaneous sampling, 12-bit plus sign resolution (effectively 13-bit dynamic range on bipolar inputs), differential inputs supporting 8VP-P true bipolar swings, internal 20ppm/1.4V reference, and a serial SPI/LVDS interface for digital output. The wide input common-mode range simplifies front-end signal conditioning when digitizing signals riding on top of varying DC offsets.
Technically, the LTC2321-12 family uses a charge-redistribution capacitive DAC core with on-chip reference buffer, achieving low aperture jitter and high SNR across the input common-mode range. Internal dithering and a high-speed comparator ratio mask integral non-linearity (INL), which is essential when digitizing small signals where DNL-induced missing codes would distort measurements.
Typical applications include motor control phase current sensing, multi-channel data acquisition systems, industrial process control, optical networking receivers, and instrumentation front-ends. The dual synchronous sampling makes it ideal for three-phase power conversion where two phase currents must be captured at exactly the same instant.
Design consideration: provide a clean low-impedance analog ground plane, place the input RC anti-alias network within 5 mm of each input pin, and bypass VDD with a 10 uF ceramic plus 0.1 uF decoupling pair to keep digital switching transients out of the analog front-end.
This page synthesizes distributor pricing, parametric alternatives, and practical design notes drawn from the Analog Devices LTC2321 datasheet family, distilled into a single reference for engineers evaluating a dual-channel 2 Msps SAR ADC for precision measurement applications.
ドロップイン代替品: LTC2321HUFD-12 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2321HUFD-12 （同一形状・フットプリント） — 相違点: Differential Input Range, Internal Reference, Number of Channels, Package, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2321IUFD-12
✅ ドロップイン✓ 在庫あり
$9.66 / 個
データシートを見る →LTC2321CUFD-12
✅ ドロップイン✓ 在庫あり
$6.1 / 個
データシートを見る →LTC2321HUFD-12#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2321HUFD-12#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2320HUFD-14
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
LTC2321HUFD-12 最大定格＆電気的特性
| Architecture | SAR (Successive Approximation Register) |
| 分解能 | 12-bit + sign (13-bit dynamic) |
| Number of Channels | 2 (dual, simultaneous sampling) |
| サンプリングレート | 2 Msps per channel |
| Input Type | Differential |
| Differential Input Range | 8 VP-P true bipolar |
| Input Common-Mode Range | Wide (per datasheet) |
| 電源電圧 | 3.3 V or 5 V single supply |
| Digital Output Interface | SPI / LVDS serial |
| Internal Reference | 20 ppm/1.4 V (per datasheet) |
| パッケージ | 28-pin QFN (4x5 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| Operating Temperature (H grade) | -40C to +125C |
| RoHS ステータス | Compliant (PBF suffix indicates lead-free) |
LTC2321HUFD-12 ピン構成
| ピン 1 | GND — Ground reference for analog and digital domains |
| ピン 2 | REF — Reference voltage pin; internal reference output |
| ピン 3 | AIN1+ — Channel 1 positive differential analog input |
| ピン 4 | AIN1- — Channel 1 negative differential analog input |
| ピン 5 | GND — Analog ground reference |
| ピン 6 | VDD — Analog supply voltage (3.3V or 5V) |
| ピン 7 | AIN2+ — Channel 2 positive differential analog input |
| ピン 8 | AIN2- — Channel 2 negative differential analog input |
| ピン 9 | GND — Ground reference |
| ピン 10 | OVDD — Digital I/O supply voltage |
| ピン 11 | GND — Digital ground reference |
| ピン 12 | SDO — Serial data output (SPI / LVDS) |
| ピン 13 | SCK — Serial clock input |
| ピン 14 | CNV — Convert input (start of conversion) |
| ピン 15 | RDL/RDY — Read/ready output indicator |
| ピン 16 | GND — Ground reference |
| ピン 17 | NC — Not connected (per datasheet) |
| ピン 18 | NC — Not connected (per datasheet) |
| ピン 19 | NC — Not connected (per datasheet) |
| ピン 20 | GND — Ground reference |
| ピン 21 | NC — Not connected (per datasheet) |
| ピン 22 | NC — Not connected (per datasheet) |
| ピン 23 | GND — Ground reference |
| ピン 24 | NC — Not connected (per datasheet) |
| ピン 25 | GND — Ground reference |
| ピン 26 | VDD — Analog supply voltage |
| ピン 27 | GND — Ground reference |
| ピン 28 | REF — Reference voltage pin (alternate connection) |
| ピン EP | EP — Exposed pad - must be soldered to analog ground for thermal dissipation |
主な用途
LTC2321HUFD-12 の用途: 7 件s: Three-Phase Motor Control Current Sensing, Multi-Channel Data Acquisition Systems, Industrial Process Control, Optical Networking Receivers, Power Inverter Phase Monitoring, Medical Instrumentation Front-Ends, Test and Measurement Instrumentation.
Three-Phase Motor Control Current Sensing
The LTC2321HUFD-12's dual simultaneous-sampling 2 Msps channels are purpose-built for field-oriented control (FOC) of three-phase motors, where two phase currents must be digitized at the exact same instant. The 8 VP-P differential input range accommodates current-shunt amplifier outputs that swing -4V to +4V around common-mode voltages up to the supply rail, eliminating the need for level shifting on the analog front-end. Compared with a sequential-sampling ADC, simultaneous sampling avoids the phase-error mismatch that would otherwise corrupt the Clarke/Park transform, keeping torque ripple under control across the full speed range.
おすすめ
Multi-Channel Data Acquisition Systems
In multi-channel data acquisition (DAQ) front-ends, the LTC2321HUFD-12 digitizes two analog channels simultaneously at 2 Msps, doubling channel density per IC and reducing BOM cost versus two separate ADCs. The 12-bit plus sign resolution provides 13 bits of dynamic range on bipolar signals, sufficient for strain-gauge bridges, thermocouple arrays after amplification, and industrial sensor multiplexing. The wide input common-mode range simplifies PCB routing when analog signals ride on different DC offsets across the acquisition board.
おすすめ
Industrial Process Control
The LTC2321HUFD-12 fits industrial process-control PLCs and DCS analog input modules where two sensor channels must be digitized per ADC to reduce board area. Its 5V single-supply operation matches legacy industrial 24V/5V-isolated architectures, while the H-grade -40C to +125C temperature range handles factory-floor thermal stress without derating the converter. The internal 20 ppm reference eliminates an external reference IC, simplifying BOM and reducing drift over the -40C to +125C span in process-control loops.
おすすめ
Optical Networking Receivers
In coherent optical receivers and burst-mode optical line terminals (OLTs), the LTC2321HUFD-12 digitizes the I and Q analog outputs of a dual-balanced photodetector transimpedance amplifier at 2 Msps, capturing in-phase and quadrature signal pairs simultaneously. The differential 8 VP-P input range and wide common-mode tolerance align directly with typical TIA output levels. SAR architecture provides deterministic sample timing, essential for downstream DSP carrier-phase recovery in coherent optical DSP ASICs.
おすすめ
Power Inverter Phase Monitoring
Solar inverters, UPS systems, and grid-tie power converters use the LTC2321HUFD-12 to monitor two AC phase currents or voltages simultaneously for power-quality analysis and protection. The 2 Msps per channel sample rate captures the fundamental 50/60 Hz AC waveform plus harmonics up to ~31 kHz with ample oversampling margin, while the 12-bit + sign dynamic range resolves both half-cycle peaks and zero-crossing transitions accurately. Differential inputs reject large common-mode dv/dt transients from the switching power stage.
おすすめ
Medical Instrumentation Front-Ends
Patient-monitoring instruments such as ECG, EEG, and pulse-oximetry front-ends benefit from the LTC2321HUFD-12's simultaneous dual-channel sampling when digitizing lead-pair signals. The 12-bit + sign resolution and 2 Msps throughput capture low-frequency bioelectric signals with sufficient headroom, while the differential input architecture provides common-mode rejection of 50/60 Hz mains interference on the patient cable. The H-grade -40C to +125C operating range supports portable medical devices used in non-climate-controlled environments.
おすすめ
Test and Measurement Instrumentation
Bench-top oscilloscopes, spectrum analyzers, and automated test equipment use the LTC2321HUFD-12 to digitize two analog channels in parallel for differential measurements and trigger-source capture. The simultaneous sampling eliminates trigger-to-acquisition skew that would otherwise appear on sequential-sampling ADCs, while the 2 Msps rate handles audio-bandwidth and low-RF applications up to ~1 MHz. Internal reference and bipolar inputs reduce external component count in cost-sensitive test instruments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2321HUFD-12 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2321IUFD-12 | LTC2321CUFD-12 | LTC2321HUFD-12#TRPBF | LTC2321HUFD-12#PBF | LTC2320HUFD-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-28 (4x5 mm) | QFN-28 (4x5 mm) - same | QFN-28 (4x5 mm) - same | QFN-28 (4x5 mm) - same | QFN-28 (4x5 mm) - same | QFN-28 (4x5 mm) - same |
| Resolution | 12-bit + sign | 12-bit + sign | 12-bit + sign | 12-bit + sign | 12-bit + sign | 14-bit + sign (+2 bits) |
| Sampling Rate | 2 Msps/channel | 2 Msps/channel | 2 Msps/channel | 2 Msps/channel | 2 Msps/channel | 1 Msps/channel (lower) |
| Operating Temperature | -40C to +125C (H grade) | -40C to +85C (I grade) | 0C to +70C (C grade) | -40C to +125C (H grade) | -40C to +125C (H grade) | -40C to +125C (H grade) |
| Input Range | 8 VP-P differential | 8 VP-P differential | 8 VP-P differential | 8 VP-P differential | 8 VP-P differential | 8 VP-P differential |
| Number of Channels | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) |
| RoHS / Lead-Free | Yes (PBF suffix) | Yes (PBF suffix) | Yes (PBF suffix) | Yes (PBF suffix) | Yes (PBF suffix) | Yes (PBF suffix) |
主な差別化要因
- True simultaneous dual-channel sampling at 2 Msps （vs Sequential-sampling ADCs of similar resolution)
- 12-bit + sign (13-bit dynamic) bipolar input without front-end level shifting （vs Unipolar-only SAR ADCs requiring input bias networks)
- Wide input common-mode range （vs ADCs with restricted common-mode input)
設計ノート
Use a continuous unbroken analog ground plane beneath the LTC2321HUFD-12 QFN-28 footprint, and solder the exposed pad (EP) directly to this plane using multiple stitching vias in the EP land pattern. Place each input RC anti-alias network within 5 mm of the AIN+ / AIN- pins; longer traces add parasitic inductance that creates aperture jitter through ground bounce. Keep digital return currents (SDO, SCK, CNV traces) physically separated from analog input traces to prevent digital-to-analogous crosstalk on sensitive 12-bit conversions.
Bypass VDD with a 10 uF X7R ceramic plus a 0.1 uF X7R ceramic placed within 2 mm of the VDD pin; provide a separate 10 uF + 0.1 uF pair on OVDD. Tie VDD and OVDD ferrite-bead separated if the digital supply is noisier than analog. Add a bulk 47 uF tantalum or polymer capacitor on the input supply rail near the ADC for transient load step absorption; the SAR architecture draws large instantaneous currents at the start of each conversion.
For best SNR, drive the AIN+ / AIN- differential inputs from a low-impedance, low-noise amplifier (op-amp bandwidth >= 10x the analog input frequency) with matched source impedances on both inputs. Mismatched input impedance creates common-mode-to-differential conversion that appears as gain error. The wide input common-mode range accommodates DC bias shifts, but AC common-mode noise above 1 MHz should still be filtered by the input RC network to avoid out-of-band aliasing into the baseband.
Do not leave REF floating - the internal reference must be bypassed with a 10 uF X7R ceramic plus 0.1 uF ceramic directly on the REF pin to prevent reference-noise-induced conversion errors. Verify the CNV signal rising edge meets the datasheet minimum pulse width; an undersized CNV pulse may not initiate conversion reliably. When operating from a 3.3V supply, ensure OVDD is tied to the same 3.3V rail so that SPI logic levels match the host controller without level shifters.
コンプライアンス情報
RoHS and REACH compliant per PBF suffix on part number; lead-free assembly per JEDEC J-STD-020. AEC-Q100 qualification status not published for this industrial-grade ADC; not intended for automotive safety-critical applications.
