MAX113CAG+TG068 - 8-Bit 400ksps 4-Ch ADC | Maxim
部品番号: MAX113CAG+TG068 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $11.92 | $11.92 |
| 10 | $10.4 | $104.00 |
| 100 | $8.95 | $895.00 |
| 500 | $7.55 | $3,775.00 |
| 1,000 | $6.59 | $6,590.00 |
MAX113CAG+TG068 概要
An 8-bit ADC (analog-to-digital converter) is a data-acquisition IC that converts continuous analog input voltages into discrete 8-bit digital codes with 256 quantization levels, providing 48 dB of theoretical dynamic range. In the system hierarchy, the MAX113 sits under Data Acquisition -> Converter -> ADC -> Mixed-Signal IC. Half-flash (also called sub-ranging flash) architectures use two 4-bit flash sections and one DAC per conversion step to halve the comparator count versus a full flash design - this reduces die area and power consumption while still reaching 400 ksps, the practical speed boundary for parallel-output ADCs of this generation.
Key features include single +3V supply operation, four single-ended analog inputs with channel selection, a hardware power-down pin that drops quiescent current to 1 microampere between conversions, and microprocessor-compatible interface logic. The half-flash engine delivers 8 bits of resolution at 400 ksps, suitable for system-monitoring loops, transducer digitizers, and portable instrumentation front-ends where low power and small PCB area matter more than 12-16 bit precision.
The half-flash core samples an input through two 4-bit flash stages back-to-back. The first stage determines the four most-significant bits and computes a 4-bit residue using an internal DAC; the second stage resolves the four least-significant bits from that residue. This two-step technique halves the comparator count from 255 to about 32, lowering both silicon cost and switching noise - the trade-off is one extra clock cycle of latency per conversion, which is invisible to most microcontrollers polling the parallel data bus.
Typical applications include handheld multimeter digitizers, portable industrial sensor front-ends, battery-powered data loggers, panel-meter readouts, and microprocessor-based control boards where multiple analog transducer signals must be read sequentially. The 1 microampere power-down current is specifically valuable for battery-management and IoT-sensor designs that wake the ADC only on demand.
When designing with this IC, place the 0.1 microfarad VDD bypass capacitor within 5 mm of the VDD pin and keep the analog input traces short and guarded to ground. The MODE pin selects the read/write bus protocol - tie it high for memory-mapped interface or low for I/O-mapped interface - so make this decision before laying out the microcontroller bus. Do not leave the reference input floating; use a low-impedance reference such as a MAX6129 or a buffered +2.5V source for specified accuracy.
This page synthesizes distributor pricing, drop-in same-package alternatives, pin-by-pin comparison, and practical design notes not collected in the manufacturer datasheet, helping engineers pick a replacement or verify second-source options without rereading twenty years of Maxim product change notices.
ドロップイン代替品: MAX113CAG+TG068 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
MAX113CAG+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX117CAG+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX113CAG+TG068 最大定格＆電気的特性
| 分解能 | 8 bit |
| Number of Input Channels | 4 |
| Conversion Architecture | Half-flash |
| サンプリングレート | 400 ksps |
| Conversion Time | 1.8 us |
| 電源電圧 | +3 V (single) |
| Power-Down Current | 1 uA |
| Input Type | Single-ended |
| Reference Type | External |
| Data Interface | Parallel (microprocessor-compatible) |
| 動作温度 | -40C to +85C |
| パッケージ | 24-SSOP (CAG) |
| 実装タイプ | Surface Mount |
| MSLレベル | 1 |
| RoHS ステータス | ROHS3 Compliant (per distributor data) |
MAX113CAG+TG068 ピン構成
| ピン 1 | AIN1 — Analog input channel 1 |
| ピン 2 | AIN2 — Analog input channel 2 |
| ピン 3 | AIN3 — Analog input channel 3 |
| ピン 4 | AIN4 — Analog input channel 4 |
| ピン 5 | REF — External reference voltage input |
| ピン 6 | AGND — Analog ground |
| ピン 7 | VDD — +3V analog supply |
| ピン 8 | DGND — Digital ground |
| ピン 9 | PWRDN — Hardware power-down (active high, 1 uA quiescent) |
| ピン 10 | MODE — Read/write mode select (high = memory-mapped, low = I/O-mapped) |
| ピン 11 | INT — Conversion-complete interrupt output |
| ピン 12 | RD — Read strobe (active low) |
| ピン 13 | WR — Write strobe (active low) |
| ピン 14 | CS — Chip select (active low) |
| ピン 15 | D0 — Data bit 0 (LSB) |
| ピン 16 | D1 — Data bit 1 |
| ピン 17 | D2 — Data bit 2 |
| ピン 18 | D3 — Data bit 3 |
| ピン 19 | D4 — Data bit 4 |
| ピン 20 | D5 — Data bit 5 |
| ピン 21 | D6 — Data bit 6 |
| ピン 22 | D7 — Data bit 7 (MSB) |
| ピン 23 | NC — Not connected (per datasheet) |
| ピン 24 | NC — Not connected (per datasheet) |
主な用途
MAX113CAG+TG068 の用途: 6 件s: Portable Industrial Sensor Front-End, Battery-Powered Data Logger, Digital Panel Meter Readout, Microprocessor-Based Control Board, Handheld Multimeter Digitizer, Audio Signal-Level Meter (Vintage / Educational).
Portable Industrial Sensor Front-End
The MAX113CAG+TG068 digitizes up to four transducer channels - typically pressure, temperature, and two analog process variables - through its four single-ended analog inputs in a single 24-SSOP footprint. The half-flash core delivers a 1.8 us conversion time (400 ksps) which is well matched to multi-channel sequential polling for PLC-style control loops at sub-kHz signal bandwidths. Power-down quiescent of 1 uA between conversions makes the part appropriate for handheld calibrators and field-service tools where battery drain between readings is critical. Reference design pattern: one external 2.5V reference (e.g., a MAX6129), four RC anti-alias filters at AIN1-AIN4, and direct 8-bit parallel connection to a microcontroller read/write bus with CS tied to an address-decoder output.
おすすめ
Battery-Powered Data Logger
Wake-on-demand data logging designs rely on the MAX113CAG+TG068's 1 uA power-down current to extend coin-cell or Li-ion runtime over multi-year deployments. The 4-channel input lets one ADC service several sensor types (temperature, humidity, light, battery voltage) without muxing - saving a separate analog switch. Half-flash conversion at 400 ksps is far above the typical environmental sample rate of 1-10 Hz, leaving the host microcontroller in deep-sleep for 99% of the duty cycle. Typical deployment: ADC power-down pin tied to a GPIO, reference held stable by a MAX6129, and the 8-bit D0-D7 bus connected to a low-power MCU such as an MSP430 or a small Cortex-M0 part. The 8-bit resolution is acceptable for general telemetry and is often read repeatedly and averaged.
おすすめ
Digital Panel Meter Readout
Front-panel digital readouts - voltmeter, ammeter, temperature indicators - use the MAX113CAG+TG068 as the conversion engine for a 3.5-digit display, where the half-flash 1.8 us conversion and the +3V single supply simplify BOM and power-rail design. Driving a multiplexed 7-segment LED or LCD display from the 8-bit parallel bus refreshes quickly without flicker. The MODE pin selects memory-mapped or I/O-mapped timing to match the chosen display controller MCU; BCD-to-7-segment drivers sit between D0-D7 and the displays. The 24-SSOP footprint is small enough to mount behind a panel display PCB. The 1 uA power-down current is irrelevant in mains-powered meters but helps battery-equipped handheld DMM designs.
おすすめ
Microprocessor-Based Control Board
Embedded control systems that read four analog feedback signals - for example, motor current, supply rail voltage, board temperature, and a user potentiometer - use the MAX113CAG+TG068 as a tight, parallel-interface digitizer. The 400 ksps throughput supports control loops up to several kHz with margin, well above the bandwidth of typical feedback signals (DC to a few hundred Hz). The microprocessor-compatible interface allows direct connection to 8051, PIC, AVR, and most Cortex-M parallel-bus modes, with the MODE pin selecting either memory-mapped or I/O-mapped access. Anti-alias RC networks at each analog input suppress switching noise from adjacent digital rails. The 8-bit resolution is more than adequate for setpoint/threshold style control rather than precision servo loops.
おすすめ
Handheld Multimeter Digitizer
Handheld digital multimeters integrate the MAX113CAG+TG068 as the analog-to-digital conversion stage behind a range-switched resistive divider and shunt network. The half-flash 1.8 us conversion is well matched to a 3 readings-per-second update cadence, and the +3V single supply lets the meter run from two AA cells with a step-up regulator. Four input channels give the meter the flexibility to digitize voltage, current, resistance (via a measured reference current), and a board-temperature-compensation channel. The 8-bit result is sufficient for a 3.5-digit display format (1999 counts) after range-scaling, and the 1 uA power-down current stretches battery life when the meter is in standby mode.
おすすめ
Audio Signal-Level Meter (Vintage / Educational)
Although the MAX113CAG+TG068's 400 ksps is far above the audio nyquist requirement of 44 ksamples/sec, the part appears in older educational lab kits and audio-level metering boards where 8-bit amplitude display is sufficient - for example, in a sound-board VU meter or a vintage-style spectrum display. Audio rectified into a DC level is fed to one or two AIN pins, the ADC result drives a bar-graph LED column, and the digital readout can be saved to a host MCU. The MAX113CAG+TG068 is not a recommended choice for hi-fi audio digitizing - for that a 16-bit sigma-delta part like the MAX1067 is preferable - but it remains a teaching example of how half-flash ADCs work in a 24-SSOP pin-compatible package.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MAX113CAG+TG068 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MAX113CAG+ | MAX117CAG+ | MAX113ENG+ |
|---|---|---|---|---|
| Brand | Analog Devices (Maxim) | Analog Devices (Maxim) | Analog Devices (Maxim) | Analog Devices (Maxim) |
| Package | 24-SSOP (CAG) | 24-SSOP (CAG) - same | 24-SSOP (CAG) - same | 24-DIP - different footprint |
| Resolution | 8 bit | 8 bit | 8 bit | 8 bit |
| Number of Input Channels | 4 | 4 | 8 (extra AIN5-8 on same package) | 4 (different package) |
| Sampling Rate | 400 ksps | 400 ksps | 400 ksps | 400 ksps |
| Conversion Time | 1.8 us | 1.8 us | 1.8 us | 1.8 us |
| Architecture | Half-flash | Half-flash | Half-flash | Half-flash |
| Supply Voltage | +3V single | +3V single | +3V single | +3V single |
| Power-Down Current | 1 uA | 1 uA | 1 uA | 1 uA |
| Lifecycle Status | Obsolete (Oct 2026) | Obsolete (Oct 2026) | Obsolete (Oct 2026) | Obsolete (Oct 2026) |
主な差別化要因
- Tape-and-reel shipping for high-volume assembly （vs MAX113CAG+)
- Doubled analog input count in same package （vs MAX117CAG+)
- Half-flash architecture vs newer SAR or sigma-delta competitors （vs MAX1067BCEE)
設計ノート
Place a 0.1 uF ceramic bypass capacitor within 5 mm of the VDD pin and a 10 uF tantalum or ceramic bulk capacitor at the supply entry point to the board. The MAX113CAG+TG068 draws up to a few milliamps during a 1.8 us conversion burst; without local bypassing the VDD droop couples into the analog inputs and degrades the lowest bits. Tie PWRDN low when the converter is active; the pin is level-sensitive and must be held low for normal operation. Use a separate analog ground star-point and route the digital return currents away from the AGND pin to avoid ground bounce appearing as ADC noise.
Keep the analog input traces (AIN1-AIN4) short and guarded on both sides by AGND copper pour to minimize digital crosstalk. Route the parallel data bus (D0-D7) and the strobe lines (RD, WR, CS) on the opposite side of the PCB from the analog section, ideally with a contiguous ground plane between them. Place the external reference bypass capacitor (typically 0.1 uF ceramic in parallel with 10 uF) directly at the REF pin because the reference input impedance is high and trace capacitance will otherwise introduce channel-dependent gain errors. Estimated: layout-following these rules typically delivers 1-2 LSB of additional effective resolution versus a 'no care' layout in 8-bit half-flash applications.
Common pitfalls include: (1) leaving the REF pin floating - the MAX113CAG+TG068 requires an external reference and will return erratic conversions if REF is unconnected; tie it to a MAX6129 2.5V or other low-noise source. (2) Driving the analog inputs beyond VDD or below AGND, which can cause latch-up; add series resistors and clamping diodes if the source can over-range. (3) Failing to honor the MODE pin - read/write timing and bus interface type depend on its logic level, so set the MODE pin before applying VDD. (4) Using PWRDN as a soft-start - it does not ramp the analog front end; wait at least the published wake-up time after de-asserting PWRDN before initiating a conversion.
Half-flash ADCs draw transient currents during the coarse and fine conversion steps, so the VDD rail sees a step load at the conversion start. Estimated: decoupling with a 0.1 uF X7R ceramic at the VDD pin reduces the VDD droop to less than 20 mV during a single conversion cycle, which is typically under the 1-LSB noise threshold for an 8-bit ADC running from a 2.5V reference. If the digital logic (CS, RD, WR) drives long traces beyond 50 mm, add 22-33 ohm series damping resistors to suppress ringing, and verify timing with the worst-case propagation delay of the chosen host bus.
コンプライアンス情報
RoHS3 compliance is confirmed via the distributor (Cytech Systems) listing on the part page as of October 2026. REACH, halogen-free status, and conflict-mineral declarations were not surfaced in the Verified Web Data and remain [DATA_NEEDED].
