MAX122ACWG - 12-Bit 500ksps ADC | Maxim Integrated | 24-SOIC
部品番号: MAX122ACWG ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $45.71 | $45.71 |
| 10 | $41.14 | $411.40 |
| 100 | $36.57 | $3,657.00 |
| 500 | $32 | $16,000.00 |
| 1,000 | $28.5 | $28,500.00 |
MAX122ACWG 概要
A successive-approximation ADC is a converter architecture that resolves an analog input one bit per clock cycle using an internal DAC and comparator, achieving high accuracy at moderate sample rates while consuming modest power. The MAX122 belongs to the broader SAR ADC family, which sits between flash ADCs (fastest, lowest resolution) and sigma-delta ADCs (highest resolution, slowest). SAR ADCs are the workhorse of industrial data acquisition, motor control, and instrumentation where deterministic latency and 10-14 bits of effective resolution are required.
Key features include 12-bit resolution, 500 ksps maximum throughput, integrated track/hold amplifier, internal 2.5 V bandgap reference, and a low-power shutdown mode that reduces supply current to microamp levels. The device accepts single-ended analog inputs up to +5 V using the internal reference, or bipolar ±5 V inputs with external circuitry. The parallel output interface simplifies memory-mapped connections to standard microcontrollers and DSPs without glue logic.
The MAX122ACWG uses a half-flash two-step architecture with on-chip calibration to deliver ±1 LSB integral nonlinearity (INL) and minimal aperture delay. The internal reference is laser-trimmed and buffered, eliminating the need for an external reference in many designs and reducing total BOM cost. The track/hold amplifier features a 4 ns acquisition time, supporting full-scale step inputs on successive conversions without losing codes.
Typical applications include industrial process control loops, multi-channel data acquisition systems using an external mux, vibration analysis, sonar/radar signal digitizers, and portable test instruments. The +5 V single-supply operation makes it compatible with legacy industrial backplanes and DSP starter kits.
When designing with this part, pay attention to analog and digital ground separation; route the REF decoupling capacitor directly to AGND with a short trace. Enable the shutdown mode via the active-low PD pin between conversion bursts to reduce average current in battery-powered monitoring applications. For best AC performance at high input frequencies, drive the analog input with a low-impedance buffer such as the MAX427 or MAX410.
This page synthesizes distributor pricing, drop-in same-package alternatives (MAX120ACWG, MAX122BCWG+, MAX122CWG+), and practical layout notes not always summarized on a single distributor page.
ドロップイン代替品: MAX122ACWG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
MAX122BCWG+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX122CWG+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX120ACWG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX122ACWG+
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX122ACWG+T
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MAX122ACWG 最大定格＆電気的特性
| 分解能 | 12 bits |
| サンプリングレート | 500 ksps |
| Number of Input Channels | 1 |
| Architecture | SAR (Successive Approximation) |
| Input Type | Single-ended |
| Analog Supply Voltage | +5 V (single) or +/-5 V (dual) |
| Digital Supply Voltage | +5 V or +/-5 V |
| Internal Reference | Yes, 2.5 V bandgap (on-chip) |
| Integral Nonlinearity (INL) | max. +/-1 LSB |
| Track/Hold Acquisition Time | 4 ns |
| Output Interface | Parallel, 12-bit, uP-compatible |
| External Clock Range | 0.1 MHz to 5 MHz |
| シャットダウン電流 | typ. 1 uA (PD pulled low) |
| パッケージ | 24-pin Wide SOIC (CWG) |
| 動作温度範囲 | 0C to +70C (commercial, A grade) |
| 入力電圧範囲 | 0 V to +5 V (unipolar) or +/-5 V with external scaling |
| RoHS ステータス | Compliant (suffix '+' versions) |
MAX122ACWG ピン構成
| ピン 1 | AIN — Analog input to track/hold |
| ピン 2 | REF — Reference voltage output / decouple |
| ピン 3 | AGND — Analog ground |
| ピン 4 | AGND — Analog ground |
| ピン 5 | DOUT0 — Parallel data output, LSB |
| ピン 6 | DOUT1 — Parallel data output |
| ピン 7 | DOUT2 — Parallel data output |
| ピン 8 | DOUT3 — Parallel data output |
| ピン 9 | DOUT4 — Parallel data output |
| ピン 10 | DOUT5 — Parallel data output |
| ピン 11 | DOUT6 — Parallel data output |
| ピン 12 | DOUT7 — Parallel data output |
| ピン 13 | DOUT8 — Parallel data output |
| ピン 14 | DOUT9 — Parallel data output |
| ピン 15 | DOUT10 — Parallel data output |
| ピン 16 | DOUT11 — Parallel data output, MSB |
| ピン 17 | DGND — Digital ground |
| ピン 18 | VDD — +5 V digital supply |
| ピン 19 | CLK — External clock input (0.1-5 MHz) |
| ピン 20 | CONVST — Conversion start (active low) |
| ピン 21 | RD — Read strobe (active low) |
| ピン 22 | CS — Chip select (active low) |
| ピン 23 | PD — Power-down (active low) |
| ピン 24 | VSS — -5 V (or GND for single-supply) |
主な用途
MAX122ACWG の用途: 6 件s: Industrial Process Control Data Acquisition, Vibration and Acoustic Signal Digitization, DSP Front-End for Motor Control, Portable Test and Measurement Instrumentation, Radar and Sonar IF Digitization, Medical Patient Monitoring.
Industrial Process Control Data Acquisition
The MAX122ACWG's 500 ksps throughput, 12-bit resolution and +/-1 LSB INL suit it for digitizing 4-20 mA or 0-10 V process signals after scaling and muxing. In a typical loop it sits behind an external analog mux (e.g., DG509) feeding a single AIN, with the parallel output latched into a microcontroller or FIFO. The single +5 V supply aligns with industrial backplanes, while the 4 ns acquisition time preserves full-scale step response when switching mux channels at rates up to 100 kHz per channel.
おすすめ
Vibration and Acoustic Signal Digitization
For vibration analyzers and acoustic digitizers, the MAX122ACWG's 500 ksps sample rate and SAR architecture provide deterministic latency that aligns with FFT block processing. When preceded by an anti-alias filter (e.g., MAX274 switched-cap biquad at 100 kHz cutoff), the ADC yields 12-bit ENOB across the audio band, making it suitable for condition-monitoring front ends on motors and bearings. Internal 2.5 V reference removes the need for an external reference IC, keeping total analog channel cost under USD 5.
おすすめ
DSP Front-End for Motor Control
In DSP-based motor control loops the MAX122ACWG digitizes phase-current feedback at 500 ksps, well above the Nyquist rate for typical 20 kHz PWM switching frequencies. Its 4 ns acquisition time handles the dI/dt spikes that occur at PWM edge transitions, and the parallel 12-bit output connects directly to a TMS320 or ADSP-21xx external bus in a single cycle. The deterministic SAR latency ensures the control law sees a sampled value whose time-stamp is exact, simplifying loop compensation.
おすすめ
Portable Test and Measurement Instrumentation
The MAX122ACWG's 1 uA shutdown current enables battery-powered DMMs and hand-held oscilloscope probes to wake on a GPIO, take a conversion burst, and return to sleep - extending battery life to months of standby. Its integrated reference and parallel interface simplify the BOM for portable data loggers that capture one-shot transient events. Operated in continuous mode at 100 ksps it consumes around 5 mA, supporting 8+ hours of operation from a 9 V alkaline cell.
おすすめ
Radar and Sonar IF Digitization
Mid-band IF stages in radar and sonar receivers can be digitized by the MAX122ACWG at the 455 kHz IF frequency, with 500 ksps providing >2x oversampling for digital filtering. The 12-bit dynamic range captures both strong target returns and weaker Doppler sidebands, while the SAR architecture's 4 ns acquisition aperture preserves phase coherence across samples - important for synthetic-aperture and phased-array signal processing.
おすすめ
Medical Patient Monitoring
The MAX122ACWG digitizes ECG, SpO2 and respiration waveforms at sampling rates from 250 sps up to 500 ksps in patient monitors and ambulatory recorders. The internal 2.5 V reference and small 24-SOIC footprint help fit the ADC into the tight analog frontend of a wearable Holter monitor, while the 1 uA shutdown mode preserves battery life during standby. Designers pair it with a low-noise instrumentation amp (e.g., MAX4100) and a digital isolator for patient-side protection.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: MAX122ACWG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | MAX122BCWG+ | MAX122CWG+ | MAX120ACWG | MAX122ACWG+ | MAX122ACWG+T |
|---|---|---|---|---|---|---|
| Brand | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) | Analog Devices (Maxim Integrated) |
| Package | 24-SOIC (CWG) | 24-SOIC (CWG) - same | 24-SOIC (CWG) - same | 24-SOIC (CWG) - same | 24-SOIC (CWG) - same | 24-SOIC (CWG) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Max Sample Rate | 500 ksps | 500 ksps | 500 ksps | 225 ksps (-55%) | 500 ksps | 500 ksps |
| Integral Nonlinearity (INL) | +/-1 LSB max | +/-0.5 LSB max (-50%) | +/-1 LSB max | +/-1 LSB max | +/-1 LSB max | +/-1 LSB max |
| Architecture | SAR | SAR | SAR | SAR | SAR | SAR |
| Channels | 1 single-ended | 1 single-ended | 1 single-ended | 1 single-ended | 1 single-ended | 1 single-ended |
| Internal Reference | 2.5 V bandgap | 2.5 V bandgap | 2.5 V bandgap | 2.5 V bandgap | 2.5 V bandgap | 2.5 V bandgap |
主な差別化要因
- Drop-in same-package B-grade precision upgrade path （vs MAX122BCWG+)
- Higher sampling rate on the same 24-SOIC footprint （vs MAX120ACWG)
- Integrated reference reduces BOM cost （vs MAX1062 (external reference))
- Deterministic SAR latency suits control loops （vs MAX1062 sigma-delta alternative)
設計ノート
Estimated: Operate MAX122ACWG from a clean +5 V analog rail decoupled with 10 uF + 0.1 uF ceramics within 5 mm of AVDD; route AGND directly to the system ground plane via a single via. Use a separate digital +5 V supply fed by a ferrite bead from AVDD when digital noise is significant, and tie DGND to the ground plane at one star point. The internal reference draws no appreciable DC current but needs 4.7 uF to AGND for low noise; do not load REF with anything more than 2 mA.
Place the input series resistor (typically 50 ohm) and RC charge bucket (100 pF) within 5 mm of the AIN pin to limit kickback from the internal track/hold switch. Keep AGND return traces wide (>= 0.5 mm) and keep digital output traces (DOUT0-DOUT11, RD, CS, CONVST) at least 5 mm from AIN and REF to avoid digital-coupling INL degradation. The 24-SOIC body length is ~12.8 mm, so plan your layout with the wider pin pitch of 1.27 mm center-to-center.
Drive AIN from a low-impedance buffer (MAX410 or MAX427 with <5 ohm output impedance) when source impedances exceed 1 kohm, since the MAX122 input draws transient current during track/hold acquisition. Estimated: with a 1 kohm source and 100 pF hold capacitor, the input sees a step whose amplitude depends on the previous code; insufficient buffer drive increases THD and degrades SNR by up to 6 dB at 100 kHz input. Hold the ADC in PD during power-up until AVDD and VDD are stable to avoid latch-up.
Do not exceed +5 V (AVDD or DVDD) or go below -5 V on any supply pin; the absolute maximum ratings in the Maxim datasheet show that the ESD clamp structure conducts at +/-10 V with permanent damage. The CONVST pin must see a falling edge with rise/fall <50 ns; if a slow uP GPIO controls it, place a Schmitt-trigger buffer between the GPIO and CONVST to guarantee the timing. The shutdown pin PD is internally pulled high with ~50 uA; tie it to DGND through a 100 kohm resistor to keep it disabled at power-up.
コンプライアンス情報
RoHS compliance applies to '+' suffixed variants (MAX122ACWG+, MAX122BCWG+, MAX122CWG+, MAX122ACWG+T). Older non-'+' variants may not be RoHS-compliant and are not recommended for new designs. AEC-Q100 qualification is not applicable; for automotive applications consider the equivalent parts from Maxim/ADI's automotive-grade portfolio.
