PCA9517ADMR2G - Level-Translating I2C Bus Repeater | onsemi
部品番号: PCA9517ADMR2G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1.12 | $1.12 |
| 10 | $1.01 | $10.10 |
| 100 | $0.84 | $84.00 |
| 500 | $0.71 | $355.00 |
| 1,000 | $0.62 | $620.00 |
PCA9517ADMR2G 概要
An I2C-bus repeater is an interface IC that sits between two segments of an I2C or SMBus system and electrically isolates them while transparently passing serial data. In the bus hierarchy it belongs to the signal buffer/repeater family of interface ICs, below the broader classes of bus transceiver and level translator. Its core job is to refresh signal edges and isolate bus capacitance so that more devices, longer traces, and larger total capacitance can be supported than a single directly driven I2C segment allows.
Key features of the PCA9517ADMR2G include two-channel bidirectional buffering that isolates capacitance between the two bus segments, integrated level translation between a low-voltage side (down to 0.9 V, for 1.0 V, 1.2 V, 1.8 V and 2.5 V logic rails) and a higher-voltage side up to 5.5 V, and support for standard and fast I2C/SMBus operating modes. An enable (EN) control allows the repeater section to be powered down or the bus to be isolated, and open-drain I2C architecture preserves wired-AND arbitration behavior on both sides.
Technically, the device uses a rise-time accelerator (keeper) on the higher-voltage side to compensate the RC loading of heavily loaded bus segments, actively pulling edges high without driving against external pull-ups. Because both channels are bidirectional without a direction pin, the part automatically follows I2C arbitration and clock stretching, which direction-controlled translators cannot do.
Typical applications include translating between a 1.8 V microcontroller I2C peripheral and a 3.3 V or 5 V sensor rail, driving long PCB traces or cable-backed bus segments in industrial control, and segmenting SMbus systems in servers and power supplies to isolate capacitance.
Design consideration: place the part close to the low-voltage controller, and size separate pull-up resistors for each bus segment - the repeater does not replace pull-ups on either side.
This page synthesizes distributor availability data, drop-in alternatives, pinout detail, and practical design notes not consolidated in the manufacturer datasheet. Pricing shown is indicative as of 2026-10-20 and should be confirmed with a quote.
ドロップイン代替品: PCA9517ADMR2G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: PCA9517ADMR2G （同一形状・フットプリント） — 相違点: Function, Package, Enable Pin, RoHS Status, Number of Channels.
クイック比較ツール — 並列比較する代替部品を選択:
PCA9517ADM
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
TCA9517DGKR
✅ ドロップイン✓ 在庫あり
$0.65 / 個
データシートを見る →TCA9517DGKRQ1
✅ ドロップイン✓ 在庫あり
$0.46 / 個
データシートを見る →PCA9517ADMR2G
✅ ドロップイン✓ 在庫あり
$0.62 / 個
データシートを見る →PCA9517ADMR2G 仕様
| 機能 | Level-Translating I2C-Bus Repeater / Buffer (ReDriver) |
| Number of Channels | 2 (bidirectional) |
| High-Voltage Side Range (VCC2) | 2.7 V to 5.5 V |
| Supported Buses | I2C-bus, SMBus |
| Capacitance Isolation | Yes (buffers both bus segments) |
| Rise-Time Accelerator | Yes (keeper on high-voltage side) |
| イネーブルピン | Yes (EN, active control) |
| 出力タイプ | Open-drain (wired-AND) |
| パッケージ | MSOP-8 (DM) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | RoHS3 Compliant |
| Prefix Suffix Code | R2G (Tape and Reel, 2.5 k units) |
PCA9517ADMR2G ピン構成
| ピン 1 | EN — Repeater enable control (power-down / bus isolation) |
| ピン 2 | GND — Ground reference |
| ピン 3 | SCL2 — Serial clock, high-voltage side (open drain) |
| ピン 4 | SDA2 — Serial data, high-voltage side (open drain) |
| ピン 5 | VCC2 — High-voltage side supply, 2.7 V to 5.5 V |
| ピン 6 | SDA1 — Serial data, low-voltage side (open drain) |
| ピン 7 | SCL1 — Serial clock, low-voltage side (open drain) |
| ピン 8 | VCC1 — Low-voltage side supply, down to 0.9 V |
主な用途
PCA9517ADMR2G の用途: 6 件s: 1.8V Microcontroller to 5V Sensor Bus Translation, Server and Telecom SMBus Segmentation, Industrial Control and PLC I/O Racks, Battery-Powered Portable and Wearable Devices, Automotive Body and Infotainment I2C Networks, Test and Measurement Instrument Backplanes.
1.8V Microcontroller to 5V Sensor Bus Translation
The PCA9517ADMR2G fits this application because its low-voltage side accepts rails down to 0.9 V with solid margin at 1.8 V, while its high-voltage side operates from 2.7 V to 5.5 V, directly bridging a 1.8 V MCU I2C port to a 5 V sensor rail in one IC. The two channels are bidirectional open-drain repeaters, so arbitration and clock stretching pass transparently without a direction pin. In use, SDA1/SCL1 connect to the MCU with pull-ups to 1.8 V, and SDA2/SCL2 connect to the 5 V sensor segment with pull-ups to 5 V; the rise-time accelerator refreshes edges on the heavily loaded sensor side. The quantified benefit is a single-chip solution replacing a discrete MOSFET translator pair, with defined thresholds and capacitive isolation that keep edge rates compliant across the full load range.
おすすめ
Server and Telecom SMBus Segmentation
Server power shelves and telecom boards chain dozens of PMBus/SMBus devices - hot-swap controllers, digital power supplies, and EEPROMs - quickly exceeding the roughly 400 pF single-segment I2C capacitance limit. The PCA9517ADMR2G fits because it buffers each channel and isolates capacitance between the management backplane segment and the local device segment, so total bus size scales with each added repeater rather than degrading edge rates. Its 5.5 V tolerant high side matches 3.3 V SMBus rails with margin, and the EN pin lets a management controller isolate a segment during fault isolation or hot-insertion. In practice, one repeater is placed at each shelf-card edge connector; the quantified benefit is that each card segment sees only its own capacitance, keeping rise times within SMBus spec across the full backplane.
おすすめ
Industrial Control and PLC I/O Racks
Industrial controllers route I2C across backplanes, long ribbon cables, and noisy environments where distributed capacitance and ground offsets corrupt marginal edges. The PCA9517ADMR2G fits because its active rise-time accelerator restores fast edges on the high-voltage side, and its buffer isolates the capacitance of cable runs from the controller-side segment. The -40C industrial temperature capability suits factory-floor racks, and the 0.9 V low side allows connection to modern low-voltage FPGAs or MCUs while the 5.5 V high side drives legacy 5 V peripherals. In use, the repeater sits at each cable boundary with per-segment pull-ups sized to the cable capacitance; the quantified benefit is an extended total bus length - each cable segment can approach the full single-segment capacitance budget independently, multiplying usable bus reach versus one directly driven line.
おすすめ
Battery-Powered Portable and Wearable Devices
Portable systems pair a 1.2 V or 1.8 V power-management MCU domain with 3.3 V sensors, fuel gauges, and touch controllers, and every microamp matters. The PCA9517ADMR2G fits because its low-voltage side operates down to 0.9 V for the newest low-core-voltage MCUs, and the EN pin allows the repeater and its downstream segment to be fully isolated during sleep states, eliminating leakage paths through pull-up networks. The bidirectional open-drain design needs no direction-switching firmware, so a single I2C master transparently services mixed-voltage devices. In use, SDA1/SCL1 connect to the low-voltage domain with 1.8 V pull-ups, and the high side powers from a rail switched only during active communication; the quantified benefit is a clean high-impedance bus state during sleep plus guaranteed thresholds at sub-1.2 V rails where simple pass-gate translators lose margin.
おすすめ
Automotive Body and Infotainment I2C Networks
Automotive ECUs distribute I2C to display bridges, ambient-light controllers, and sensor satellites along harness lengths that far exceed consumer bus budgets. The PCA9517A function fits because the repeater refreshes edges and segments capacitance at each module boundary, and for AEC-Q1-qualified designs the footprint-compatible TCA9517DGKRQ1 allows the same layout to be reused. The EN pin supports module-level bus isolation for diagnostics and low-power modes, and the 5.5 V high side tolerates automotive 5 V rails with load-dump margin on regulated supplies. In use, one repeater per harness connector splits the network into independently sized segments with per-segment pull-ups; the quantified benefit is deterministic rise times across temperature and load - each segment's capacitance is isolated, preventing a heavily loaded body-controller harness from invalidating edges on the infotainment head unit segment.
おすすめ
Test and Measurement Instrument Backplanes
Bench instruments and modular measurement systems hang calibration EEPROMs, digitizers, and fan controllers off shared I2C segments routed across large PCBs where trace capacitance alone can approach bus limits. The PCA9517ADMR2G fits because its two-channel buffer splits the backplane into a controller segment and a peripheral segment, each with its own capacitance budget and optimized pull-ups, while the rise-time accelerator compensates residual loading. The 0.9 V low side interfaces directly to low-voltage FPGA bank rails used in modern instruments, and the 5.5 V high side supports legacy 5 V modules. In use, repeaters are placed at the backplane-to-module boundary; the quantified benefit is that mixed-voltage, mixed-load module populations coexist on one logical bus without manual edge tuning - measured rise times stay within spec regardless of how many modules are populated.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: PCA9517ADMR2G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | PCA9517ADM | TCA9517DGKR | TCA9517DGKRQ1 | PCA9517ADMR2G (NXP) |
|---|---|---|---|---|---|
| Package | MSOP-8 (DM) | MSOP-8 (DM) - same | VSSOP-8 (MSOP-8) - same | VSSOP-8 (MSOP-8) - same | MSOP-8 (DM) - same |
| Brand | onsemi | onsemi | Texas Instruments | Texas Instruments | NXP Semiconductors |
| Channels | 2 bidirectional | 2 bidirectional | 2 bidirectional | 2 bidirectional | 2 bidirectional |
| High-Voltage Side Maximum | 5.5 V | 5.5 V | 5.5 V | 5.5 V | 5.5 V |
| Enable Pin | Yes (EN) | Yes (EN) | Yes (EN) | Yes (EN) | Yes (EN) |
| Automotive Qualification | No (standard grade) | No | No | Yes (AEC-Q1) | No |
| Buses Supported | I2C, SMBus | I2C, SMBus | I2C, SMBus | I2C, SMBus | I2C, SMBus |
主な差別化要因
- 0.9 V low-side operation for the newest low-voltage MCUs （vs PCA9517ADM)
- Same-function alternative with automotive qualification available in the same footprint （vs TCA9517DGKRQ1)
- Capacitive isolation, unlike passive MOSFET translators （vs NVT2002DP,118)
設計ノート
Provide separate pull-up resistor networks on BOTH bus segments - the PCA9517ADMR2G is an open-drain repeater and does not drive the bus high internally (the rise-time accelerator only assists edges on the high-voltage side). Size each segment's pull-ups to that segment's total capacitance: lower values (roughly 1 kOhm to 2.2 kOhm at 3.3 V) for heavily loaded cable-backed segments, higher values (4.7 kOhm to 10 kOhm) for short lightly loaded segments. Place the repeater close to the boundary between segments, typically the cable or backplane connector.
Use the EN pin for power sequencing: during system power-up, hold EN low until both VCC1 and VCC2 are stable, otherwise the repeater can back-power unpowered slave devices through the pull-up networks and cause bus lockup. Also verify your low-side rail against the device's minimum: the A-version supports down to 0.9 V, but if your rail is 1.0 V or 1.2 V, confirm threshold margins in the datasheet electrical characteristics table for your exact temperature range rather than assuming datasheet typical values apply at -40C.
Keep SDA/SCL trace stubs on the high-capacitance side as short as possible after the repeater and route them as a matched pair away from switching-node or clock aggressors - although I2C is slow (up to fast-mode rates), the rise-time accelerator is sensitive to capacitive coupling and an under-damped long stub can cause ringing that double-triggers edge detection. Add 0.1 uF ceramic decoupling capacitors at both VCC1 and VCC2 pins, placed within 2 mm of the pins, plus a bulk 1 uF per rail on segment-heavy boards.
When cascading multiple repeaters, remember that each adds a small propagation delay and edge-restoration stage. For long daisy-chained topologies (backplane + several cards), keep the total number of cascaded repeater stages low and verify rise/fall times and bus-free time (tBUF) at the farthest slave with an oscilloscope at maximum load and minimum temperature. Estimated: at standard-mode 100 kHz, 2-3 cascaded stages remain comfortably within I2C timing margins; validate empirically for fast-mode 400 kHz designs.
コンプライアンス情報
RoHS3 compliant and lead-free per distributor listings (DigiKey/DiGi Electronics). REACH, halogen-free, and conflict-minerals status should be confirmed via the onsemi material declaration report.
