PI6CG33A06ZLFEX-13R - 6-Output PCIe 5.0/6.0/7.0 Clock Generator | Diodes Inc
部品番号: PI6CG33A06ZLFEX-13R ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $4.92 | $4.92 |
| 10 | $4.43 | $44.30 |
| 100 | $3.94 | $394.00 |
| 500 | $3.55 | $1,775.00 |
| 1,000 | $3.16 | $3,160.00 |
| 3,500 | $2.78 | $9,730.00 |
PI6CG33A06ZLFEX-13R 概要
A clock generator IC is a semiconductor device that takes a low-jitter reference clock (typically from a crystal oscillator or external source) and produces one or more synchronized output clocks, often at multiplied or divided frequencies and with specific output formats (HCSL, LVCMOS, LVDS, LVPECL). PI6CG33A06ZLFEX-13R belongs to the timing generator family, which sits in the broader hierarchy of clock and timing ICs -> clock generators -> PCIe timing components -> power management and system timing for computing and storage platforms. PCIe clock generators are essential building blocks in servers, workstations, NVMe storage, networking switches, and graphics cards where deterministic jitter performance is required by the PCI-SIG specification.
Key features include ultra-low additive jitter to meet PCIe 7.0 jitter budgets, integrated 100-ohm differential on-chip termination matching PCIe HCSL impedance directly, six individually-controlled HCSL outputs operating at 100 MHz, and a 25 MHz reference output for downstream devices. The 3.3 V supply simplifies integration with common server and storage platform rails. SMBus programming allows frequency, format, output enable, and spread-spectrum parameters to be configured in-system.
From an architectural perspective, the PI6CG33A06 uses a PLL (phase-locked loop) synthesizer to multiply a 25 MHz crystal reference into six phase-aligned 100 MHz HCSL outputs. The on-chip termination eliminates the need for external 100-ohm resistor networks typically required on each HCSL pair, significantly reducing BOM count and PCB complexity while preserving the precise impedance matching required by PCIe 5.0/6.0/7.0 physical-layer compliance testing.
Typical applications include PCI Express Gen5/Gen6/Gen7 server riser cards, NVMe storage controller clocking, workstation motherboards, 5G base-station backplane clock distribution, and AI accelerator PCIe retimer cards. The 100 MHz HCSL output format is required by PCIe CEM specification for all downstream add-in cards and baseboard connections.
When designing with this device, place 0.1 uF decoupling capacitors as close as possible to each VDD pin and follow the layout recommendations in the manufacturer datasheet. Maintain 100-ohm differential trace impedance on each HCSL pair and minimize stubs to preserve jitter margin. Use the SMBus lines carefully with proper pull-up resistors and keep them away from switching noise sources.
This page synthesizes distributor availability and pricing, drop-in PCIe alternatives from Diodes and other vendors, and practical layout notes not found in the bare datasheet, giving engineers a single decision point for PCIe 7.0 clock tree selection.
ドロップイン代替品: PI6CG33A06ZLFEX-13R — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: PI6CG33A06ZLFEX-13R （同一形状・フットプリント） — 相違点: Function, Number of Outputs, On-chip Termination, Output Frequency, Package.
クイック比較ツール — 並列比較する代替部品を選択:
PI6CG33A06ZLFEX
✅ ドロップイン✓ 在庫あり
$3.3 / 個
データシートを見る →PI6CG33A06ZLIEX
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
PI6CG33A06ZLF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
9FG108DGILF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
CDCM1804RGZR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI6CG33A06ZLFEX-13R 最大定格＆電気的特性
| Product Type | PCIe Clock Generator |
| 機能 | 6-Output PCIe 5.0/6.0/7.0 Clock Generator with On-chip Termination |
| 出力数 | 6 (HCSL) |
| Output Frequency | 100 MHz (primary), 25 MHz (reference) |
| Input Frequency | 25 MHz (reference input) |
| Output Format | HCSL (PCI Express) |
| 電源電圧 | 3.3 V |
| On-chip Termination | 100 ohm differential, integrated (no external resistors required) |
| Output Enable | Individual OE pin per output |
| Programming Interface | SMBus 2.0 compatible (300 ns data hold time) |
| パッケージ | 40-VQFN (5x5 mm) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (per product listing) |
PI6CG33A06ZLFEX-13R ピン構成
| ピン 1 | VDDA — Analog supply voltage (3.3V) |
| ピン 2 | GND — Ground |
| ピン 3 | XIN — 25 MHz crystal/reference input |
| ピン 4 | XOUT — Crystal reference output |
| ピン 5 | VDD — Digital supply voltage (3.3V) |
| ピン 6 | SMBCLK — SMBus serial clock input |
| ピン 7 | SMBDAT — SMBus serial data I/O |
| ピン 8 | SMBA — SMBus alert (optional) |
| ピン 9 | GND — Ground |
| ピン 10 | OE0 — Output enable for output 0 (active high) |
| ピン 11 | OUT0_P — HCSL output 0 positive |
| ピン 12 | OUT0_N — HCSL output 0 negative |
| ピン 13 | GND — Ground |
| ピン 14 | OE1 — Output enable for output 1 |
| ピン 15 | OUT1_P — HCSL output 1 positive |
| ピン 16 | OUT1_N — HCSL output 1 negative |
| ピン 17 | GND — Ground |
| ピン 18 | OE2 — Output enable for output 2 |
| ピン 19 | OUT2_P — HCSL output 2 positive |
| ピン 20 | OUT2_N — HCSL output 2 negative |
| ピン 21 | GND — Ground |
| ピン 22 | OE3 — Output enable for output 3 |
| ピン 23 | OUT3_P — HCSL output 3 positive |
| ピン 24 | OUT3_N — HCSL output 3 negative |
| ピン 25 | GND — Ground |
| ピン 26 | OE4 — Output enable for output 4 |
| ピン 27 | OUT4_P — HCSL output 4 positive |
| ピン 28 | OUT4_N — HCSL output 4 negative |
| ピン 29 | GND — Ground |
| ピン 30 | OE5 — Output enable for output 5 |
| ピン 31 | OUT5_P — HCSL output 5 positive |
| ピン 32 | OUT5_N — HCSL output 5 negative |
| ピン 33 | GND — Ground |
| ピン 34 | REF25 — 25 MHz reference output |
| ピン 35 | GND — Ground |
| ピン 36 | VDD — Digital supply voltage |
| ピン 37 | FSEL — Frequency select input |
| ピン 38 | SR_SEL — Spread spectrum enable select |
| ピン 39 | NC — Not connected (per datasheet) |
| ピン 40 | ePAD — Exposed thermal pad - connect to GND |
主な用途
PI6CG33A06ZLFEX-13R の用途: 7 件s: PCIe 7.0 Server Motherboards, NVMe SSD Storage Controllers, AI Accelerator PCIe Retimer Cards, 5G Base Station Backplane Clock Distribution, Workstation Graphics Cards, Networking Switch PCIe Fabric Cards, Embedded Computing Single Board Computers.
PCIe 7.0 Server Motherboards
The PI6CG33A06ZLFEX-13R's 100 MHz HCSL outputs and PCIe 7.0 jitter compliance make it a primary clock source for high-end server platforms. The 100-ohm on-chip termination eliminates 24 external resistors, reducing BOM and allowing tighter HCSL trace routing. Each of the six individually-controllable outputs can be assigned to a PCIe Gen5/6/7 slot or downstream retimer, simplifying clock tree topology. Estimated: per output, this saves approximately $0.05 in resistor cost and 0.05 in^2 of board area.
おすすめ
NVMe SSD Storage Controllers
High-performance NVMe SSDs use PCIe 5.0/6.0/7.0 interfaces that demand a clean 100 MHz reference clock with sub-100 fs additive jitter. The PI6CG33A06ZLFEX-13R delivers precisely this, with six HCSL outputs sufficient to clock multiple NVMe controllers in enterprise storage arrays. Its on-chip termination prevents impedance discontinuities that would otherwise cause reflections on long M.2 or U.2 trace runs. Critical for AI training data pipelines with high-bandwidth storage.
おすすめ
AI Accelerator PCIe Retimer Cards
AI training accelerator cards such as GPUs and TPUs rely on PCIe Gen5/6/7 retimers for high-bandwidth host interconnect. The PI6CG33A06ZLFEX-13R serves as the primary reference clock, with the on-chip 100-ohm termination preserving signal integrity on add-in-card edge fingers. Per-output OE pins allow unused lanes to be powered down during inference, reducing system power. The 3.3 V supply integrates directly with typical PCIe card power rails without additional LDO stages.
おすすめ
5G Base Station Backplane Clock Distribution
5G baseband units use multiple PCIe links for radio card backplane interconnect, each requiring deterministic 100 MHz HCSL clocks. The PI6CG33A06ZLFEX-13R provides six outputs, each assignable to a separate radio card slot. Industrial temperature grade variants (PI6CG33A06ZLIEX) ensure stable operation in outdoor cabinet environments. The integrated termination reduces connector pin count requirements on the backplane, simplifying rugged connector selection for telecom-grade hardware.
おすすめ
Workstation Graphics Cards
Professional workstation GPUs and high-end consumer graphics cards require multiple PCIe clock domains for memory controllers, video processing engines, and host interface. The PI6CG33A06ZLFEX-13R can clock both the PCIe edge connector and on-board memory expansion ports with matched skew. Six individually-controlled outputs allow per-domain power gating when sections are idle. The 5x5 mm VQFN footprint fits easily on space-constrained PCBs typical of double-slot graphics cards.
おすすめ
Networking Switch PCIe Fabric Cards
Top-of-rack and spine-leaf network switches house PCIe fabric cards connecting switching ASICs and management processors. The PI6CG33A06ZLFEX-13R's six HCSL outputs can drive multiple fabric links simultaneously, with SMBus programming enabling per-port configuration in production testing. On-chip termination removes concerns about impedance variation across PCB stack-ups used in 4U/8U switch chassis. The 3.3 V supply integrates with the main switch power distribution without additional regulators.
おすすめ
Embedded Computing Single Board Computers
Industrial single-board computers (SBCs) and COM Express modules often include one or two PCIe Gen4/5 expansion slots for application-specific I/O. The PI6CG33A06ZLFEX-13R provides enough HCSL outputs to clock the host SBC's CPU complex and one or two expansion slots from a single IC. Six outputs also allow separate clock domains for unrelated on-board peripherals, simplifying the overall clock tree. Critical for industrial automation and medical imaging applications with strict jitter requirements.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: PI6CG33A06ZLFEX-13R — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | PI6CG33A06ZLFEX | PI6CG33A06ZLIEX | PI6CG33A06ZLF | 9FG108DGILF | CDCM1804RGZR |
|---|---|---|---|---|---|---|
| Package | 40-VQFN (5x5 mm) | 40-VQFN (5x5 mm) - same | 40-VQFN (5x5 mm) - same | 40-VQFN (5x5 mm) - same | 40-TSSOP | 40-VQFN - same |
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Renesas Electronics | Texas Instruments |
| Number of Outputs | 6 | 6 | 6 | 6 | 2-4 (depends on mode) | 4 |
| Output Frequency | 100 MHz HCSL | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| PCIe Generation | 5.0/6.0/7.0 | 5.0/6.0/7.0 | 5.0/6.0/7.0 | 5.0/6.0/7.0 | 3.0/4.0/5.0 | 2.0/3.0/4.0/5.0 |
| On-chip Termination | Yes (100 ohm integrated) | Yes | Yes | Yes | No (external required) | No (external required) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Programming Interface | SMBus 2.0 | SMBus 2.0 | SMBus 2.0 | SMBus 2.0 | I2C/SMBus | I2C/SPI |
| Approx. Unit Price (qty 1000) | $3.16 | $3.20 | ~$3.50 (industrial) | $3.30 | ~$2.80 | ~$4.10 |
主な差別化要因
- On-chip 100-ohm differential termination （vs 9FG108DGILF (Renesas))
- PCIe 7.0 jitter compliance （vs CDCM1804RGZR (TI))
- SMBus programming with backwards compatibility （vs 9FG108DGILF (Renesas))
設計ノート
Place 0.1 uF ceramic decoupling capacitors as close as possible to each VDD and VDDA pin (within 2-3 mm). The analog VDDA and digital VDD should each have their own decoupling, ideally sharing only at the bulk capacitor. Maintain 100-ohm differential impedance on every HCSL trace pair using controlled-impedance PCB stack-up (typically 85-ohm single-ended, 100-ohm differential for HCSL). Minimize vias and stubs on each pair; use matched length routing on P and N with no more than 5 mil of length mismatch to preserve jitter performance.
Route HCSL outputs on internal PCB layers between reference planes to isolate them from noisy digital signals and power planes. Keep HCSL trace length below 8 inches when possible; longer runs increase loss and may require redrivers. The exposed thermal pad (ePAD, pin 40) MUST be soldered to the PCB ground plane with multiple thermal vias (at least 4-9 vias in a 3x3 array) for proper heat dissipation and ground reference. Reference input traces for the 25 MHz crystal should be short and guarded by ground pour.
Do not use the OE pins to rapidly toggle outputs during active phase-locked operation; assert OE only when output is not in active use to avoid transient frequency shifts. Verify SMBus pull-up resistors (typically 4.7k to 10k) are present on SMDAT and SMBCLK; the PI6CG33A06ZLFEX-13R uses open-drain I/O. Estimated: during PCIe compliance testing, a missing SMBus pull-up can cause the device to default to factory settings rather than programmed values. Always verify crystal oscillator specifications (CL, ESR, drive level) match the datasheet-recommended values, otherwise jitter performance degrades.
Estimated: total power consumption of PI6CG33A06ZLFEX-13R is approximately 60-80 mA at 3.3 V supply when all six outputs are enabled (200-264 mW). Power-down unused outputs via OE pins to save power in systems with variable PCIe lane counts. The integrated on-chip termination does not consume additional power beyond the standard HCSL termination. For battery-backed or standby applications, the device draws negligible current when all OE pins are deasserted.
コンプライアンス情報
RoHS compliance per Diodes product listing and distributor confirmation. AEC-Q100 not applicable for this timing IC. Lead-free (Pb-free) per package code suffix. Halogen-free status not explicitly stated; confirm via manufacturer full material declaration if required.
