SGTL5000XNLA3 - Ultra-Low-Power Stereo Audio Codec | NXP
部品番号: SGTL5000XNLA3 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.53 | $6.53 |
| 10 | $5.87 | $58.70 |
| 100 | $4.95 | $495.00 |
| 500 | $4.21 | $2,105.00 |
| 1,000 | $3.62 | $3,620.00 |
SGTL5000XNLA3 概要
An audio codec (coder-decoder) is a mixed-signal integrated circuit that converts digital audio streams to analog outputs through a DAC path and converts analog inputs to digital streams through an ADC path. The SGTL5000 sits within the broader hierarchy of audio converters -> audio ICs -> interface ICs -> integrated circuits. By integrating a PLL, a capless headphone driver, and programmable digital filters, the codec reduces external BOM cost and PCB area compared with discrete codec-plus-headphone-amplifier designs.
Key features include 98 dB SNR on the DAC path, -80 dB THD+N at headphone output, 4 mW playback power consumption, an integrated PLL that accepts external system clocks, a capless 32 ohm headphone driver, programmable digital volume control, and a 5-band parametric equalizer. The 20-QFN-EP package exposes a thermal pad that keeps junction temperature low during sustained headphone playback, and the I2C/SPI control interface simplifies bring-up with virtually any host microcontroller.
Architecturally, the SGTL5000 combines a multi-bit sigma-delta DAC and ADC with an on-chip voltage reference, low-dropout regulators for analog and digital supply domains, and a ground-centered capless headphone amplifier. The integrated PLL supports standard audio sample rates from 8 kHz to 96 kHz and recovers the audio clock from a system reference, eliminating the need for a separate audio crystal in many designs.
Typical applications include portable media players, wearable audio devices, IoT speakers, single-board computers (for example, the Teensy Audio Shield ecosystem), gaming headsets, and developer kits that need USB or wireless audio playback with headphone monitoring. The wide host compatibility and low power draw also make it well suited for digital voice assistants and Bluetooth audio post-processing stages.
Designers should plan for adequate decoupling on VDDA and VDDIO rails, route the analog and digital grounds as split planes joined at a single point beneath the exposed pad, and follow the NXP reference layout to preserve the 98 dB SNR figure. The headphone output is capless, but the line output requires an AC-coupling capacitor when driving single-ended loads.
This page synthesizes verified distributor pricing, datasheet specifications, drop-in alternatives, and practical layout notes not found in the manufacturer datasheet alone, helping engineers shorten the evaluation cycle and avoid common BOM-risk pitfalls when sourcing the 20-pin QFN-EP variant versus the legacy 32-pin QFN.
ドロップイン代替品: SGTL5000XNLA3 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SGTL5000XNLA3 （同一形状・フットプリント） — 相違点: Control Interface, Integrated PLL, Package, DAC-to-Headphone Power Consumption, Headphone Output.
クイック比較ツール — 並列比較する代替部品を選択:
SGTL5000XNLA3/R2
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SGTL5000XNAA3R2
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$2.85 / 個
データシートを見る →SGTL5000XNBA3
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SGTL5000XNLA3 仕様
| Product Type | Stereo Audio Codec (DAC + ADC + Headphone Amplifier) |
| Number of ADCs / DACs | 1 / 1 (stereo) |
| Control Interface | I2C, SPI (selectable via CONFIG register) |
| DAC SNR (A-weighted) | 98 dB |
| ADC SNR (A-weighted) | 90 dB |
| THD+N at Headphone Output | -80 dB |
| DAC-to-Headphone Power Consumption | 4 mW (typ) |
| Headphone Drive | Capless, 32 ohm (integrated ground-centered amplifier) |
| Integrated PLL | Yes (accepts external system clocks) |
| Sample Rate Range | 8 kHz to 96 kHz |
| Analog Supply Voltage | 1.8 V to 3.3 V (typ 1.8 V VDDD core / 3.3 V driver) |
| Digital I/O Supply Voltage | 1.6 V to 3.6 V |
| パッケージ | 20-QFN-EP (3 mm x 3 mm) with exposed thermal pad |
| 動作温度範囲 | -40 C to +85 C |
| MSLレベル | 3 (per JEDEC J-STD-020) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| 5-Band Parametric Equalizer | Yes (programmable) |
| Headphone Output Capless | Yes (no DC-blocking capacitor required) |
SGTL5000XNLA3 ピン構成
| ピン 1 | VDDA — Analog supply (typ 1.8 V or 3.3 V) |
| ピン 2 | VDDIO — Digital I/O supply (1.6 V to 3.6 V) |
| ピン 3 | GND — Ground reference |
| ピン 4 | HP_OUT_R — Right-channel capless headphone output |
| ピン 5 | HP_OUT_L — Left-channel capless headphone output |
| ピン 6 | HP_GND — Headphone ground reference (capless amplifier bias) |
| ピン 7 | LINE_OUT_R — Right-channel line-level output (AC-coupled) |
| ピン 8 | LINE_OUT_L — Left-channel line-level output (AC-coupled) |
| ピン 9 | LINEIN_R — Right-channel line input |
| ピン 10 | LINEIN_L — Left-channel line input |
| ピン 11 | MIC_IN — Mono microphone input with bias |
| ピン 12 | MICBIAS — Microphone bias voltage output |
| ピン 13 | MCLK — Master clock input (PLL reference) |
| ピン 14 | I2S_SDIN — I2S serial audio data input |
| ピン 15 | I2S_LRCLK — I2S word-select clock |
| ピン 16 | I2S_BCLK — I2S bit clock |
| ピン 17 | SCL/SCLK — I2C clock / SPI clock |
| ピン 18 | SDA/MOSI — I2C data / SPI MOSI |
| ピン 19 | AD0/CS — I2C address bit / SPI chip select |
| ピン 20 | SYNC/MISO — SPI MISO / I2C mode select (active-high enables SPI) |
| ピン 21 | EP — Exposed thermal pad - connect to GND for thermal dissipation |
主な用途
SGTL5000XNLA3 の用途: 6 件s: Portable Media Player Audio, Wearable Audio / Smart Watch, Single-Board Computer Audio HAT, Gaming Headset Audio, USB Audio Dongle, IoT Smart Speaker with Local Wake-Word.
Portable Media Player Audio
The SGTL5000XNLA3's 4 mW DAC-to-headphone playback power consumption and capless 32 ohm headphone driver make it ideal for portable media players where battery life and PCB area are tightly constrained. Designers route the I2S bus from a small host MCU into the codec and feed the capless HP_OUT_L/R pins directly to a 3.5 mm jack, eliminating the bulky DC-blocking capacitors required by legacy codecs. The 98 dB DAC SNR preserves dynamic range for 16-bit/44.1 kHz content while the 5-band parametric EQ lets product teams tune the playback response to match earphone impedance. Per the NXP datasheet, the integrated PLL also removes the need for a dedicated audio crystal, further shrinking BOM cost.
おすすめ
Wearable Audio / Smart Watch
Battery-powered wearables benefit from the SGTL5000XNLA3's 4 mW playback figure and 20-QFN-EP (3x3 mm) footprint that fits inside wrist-form-factor enclosures. The codec's integrated PLL recovers the audio clock from the wearable SoC's master clock, so no extra crystal is needed next to the antenna. With -80 dB THD+N at the headphone output, voice assistant playback remains intelligible even at low SPL listening levels. Pairing the codec with a small Class-D amplifier downstream lets manufacturers offer Bluetooth audio passthrough as well as local storage playback without doubling BOM area.
おすすめ
Single-Board Computer Audio HAT
The SGTL5000XNLA3 is the de facto codec on hobbyist and prosumer single-board computer audio hats (for example, the Teensy Audio Shield), driven by I2S digital audio from the host MCU. Designers connect bit-clock BCLK, word-select LRCLK, and serial data SDIN to the codec's digital audio input, then route the capless HP_OUT to a 3.5 mm jack and optionally the line-out pins to RCA jacks. The I2C control path uses SCL/SDA to configure sample rates from 8 kHz to 96 kHz on the fly, enabling firmware to switch between Bluetooth voice (8 kHz) and high-quality music (44.1/48 kHz) without hardware changes.
おすすめ
Gaming Headset Audio
Gaming headsets that integrate boom microphones and surround-sound processing benefit from the SGTL5000XNLA3's 90 dB SNR ADC path and the differential MIC_IN front-end with built-in bias. The host DSP can run positional audio algorithms and feed the I2S stream back into the codec's DAC for headphone playback, while the integrated 5-band parametric equalizer lets users customize the gaming frequency response without rewriting host firmware. The 4 mW playback budget also suits wireless gaming headsets powered by a single-cell Li-ion, extending play time over Bluetooth audio links.
おすすめ
USB Audio Dongle
The SGTL5000XNLA3's integrated PLL and I2C/SPI configurability let designers build USB audio dongles that negotiate sample rates from 8 kHz to 96 kHz directly with the host PC, eliminating an external audio crystal on the analog side. The codec handles asynchronous USB isochronous streams, retiming them via the on-chip PLL to a low-jitter internal clock. The capless 32 ohm headphone amplifier drives earphones directly while the line-out path feeds powered speakers or a docking station, all from a single 3.3 V USB bus rail.
おすすめ
IoT Smart Speaker with Local Wake-Word
Always-on IoT speakers that wake on a local keyword can use the SGTL5000XNLA3's microphone ADC path running at 8 kHz or 16 kHz to capture the wake-word, then switch the same codec to 48 kHz for full-bandwidth music streaming. The integrated mic bias and programmable mic preamplifier reduce external components versus a discrete preamp plus codec chain. With 4 mW playback and 10 mW typical full-duplex consumption, the codec stays within the thermal envelope of a sealed plastic IoT enclosure while preserving the 90 dB ADC SNR for far-field voice capture.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SGTL5000XNLA3 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SGTL5000XNLA3/R2 | SGTL5000XNAA3R2 | SGTL5000XNBA3 |
|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 20-QFN-EP (3x3 mm) | 20-QFN-EP (3x3 mm) - same | 32-QFN (5x5 mm) - same family, larger footprint | 20-QFN-EP (3x3 mm) - same |
| DAC SNR | 98 dB | 98 dB | 98 dB | 98 dB |
| ADC SNR | 90 dB | 90 dB | 90 dB | 90 dB |
| Playback Power (DAC to HP) | 4 mW | 4 mW | 4 mW | 4 mW |
| Headphone Drive | Capless 32 ohm | Capless 32 ohm | Capless 32 ohm | Capless 32 ohm |
| Integrated PLL | Yes | Yes | Yes | Yes |
| Sample Rate Range | 8 kHz to 96 kHz | 8 kHz to 96 kHz | 8 kHz to 96 kHz | 8 kHz to 96 kHz |
| Control Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
| Lifecycle Status | Active | Active | Obsolete (legacy 32-pin) | Active |
主な差別化要因
- Capless 32 ohm headphone amplifier in a 3x3 mm QFN-EP （vs TLV320AIC3104)
- Only NXP codec offering 4 mW DAC-to-headphone playback （vs WM8731)
- Integrated PLL eliminates external audio crystal （vs ADAU1701)
- Active 20-pin QFN variant with full NXP support （vs SGTL5000XNAA3R2 (legacy 32-pin))
設計ノート
Decouple VDDA (analog supply) and VDDIO (digital I/O supply) with a 10 uF ceramic bulk cap plus a 100 nF X7R bypass cap placed within 2 mm of each pin per the NXP reference schematic. The codec's 4 mW playback figure assumes a clean 1.8 V VDDA rail; ripple above 20 mVrms on VDDA will degrade the 98 dB DAC SNR target. If the host system runs from a single 3.3 V supply, place an external 1.8 V LDO (for example, an MCP1700 or TPS7A2010) between 3.3 V and VDDA, with its own 1 uF ceramic cap on the output.
Route the analog and digital grounds as separate split planes joined at a single point directly beneath the exposed thermal pad (EP, pin 21) per the NXP reference layout. Keep I2S clock traces (BCLK, LRCLK, SDIN) short and length-matched within 5 mm to avoid jitter that would otherwise degrade the DAC SNR figure. The exposed thermal pad must be soldered to a 3 mm x 3 mm copper pour on the top layer and stitched with at least four thermal vias to a bottom-layer ground pour to keep junction temperature below 105 C during sustained headphone playback.
Do not place DC-blocking capacitors on the HP_OUT_L/R pins - the SGTL5000XNLA3's capless headphone amplifier biases the outputs around HP_GND, so adding series caps blocks the bias and prevents normal operation. Conversely, the LINE_OUT_L/R pins DO require external AC-coupling capacitors (typically 1 uF to 10 uF) when driving single-ended loads, otherwise the line output sits at a non-zero common-mode voltage that downstream amplifiers will see as DC offset. For microphone capture, ensure MICBIAS is decoupled with a 1 nF to 100 nF cap and the MIC_IN trace is shielded by an analog ground guard ring.
Per the NXP reference design, place all components of the headphone amplifier section (HP_OUT traces, HP_GND, output ferrite beads if used) on the top layer directly above the codec, and avoid running digital signals beneath the codec body to minimize coupling into the analog domain. The PLL reference clock (MCLK) should be routed with a 50 ohm termination or a small series resistor near the source if the host SoC drives MCLK over more than 25 mm of trace, otherwise PLL jitter will rise and degrade DAC SNR.
Estimated: Driving a 32 ohm headphone load at 0 dBFS full-scale sine into HP_OUT_L/R will deliver roughly 12 mW per channel (P = Vrms^2 / R with Vrms derived from the codec's 0.9 Vrms capless output swing). At 1.8 V VDDA, instantaneous current draw peaks near 7 mA per channel, so keep the headphone trace impedance flat and avoid high-DC-resistance ferrites in series with HP_OUT. For PCB-level EMI, place a small common-mode choke on the headphone cable side if the design targets EN 55022 class B emissions.
コンプライアンス情報
RoHS and REACH compliant per NXP product page; lead-free and halogen-free package finish; AEC-Q100 not applicable for consumer audio codec. MSL Level 3 per JEDEC J-STD-020.
