SI53323-B-GM - 2:4 LVPECL 1.25 GHz Clock Buffer | Skyworks
部品番号: SI53323-B-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $9.1 | $9.10 |
| 10 | $8.46 | $84.60 |
| 100 | $7.59 | $759.00 |
| 500 | $6.85 | $3,425.00 |
| 1,000 | $6.07 | $6,070.00 |
SI53323-B-GM 概要
A clock buffer (also called a clock fanout buffer or clock driver) is a specialized digital IC that receives a single clock reference and replicates it onto multiple outputs with low additive jitter, deterministic skew, and controlled impedance. In the broader signal-chain hierarchy it sits between the frequency source (crystal, PLL, or oscillator) and the loads it serves (FPGAs, ASICs, transceivers, ADCs/DACs). Compared to a PLL or frequency synthesizer, a clock buffer does not change frequency - its job is distribution fidelity, which is exactly what the SI53323-B-GM is optimized for.
The SI53323-B-GM uses advanced CMOS technology to fan out 4 differential LVPECL copies of one selected input with minimal additive jitter (sub-ps RMS typical) and very low propagation-delay variability across process, voltage and temperature. Independent VDD/V core and output-bank supply pins allow on-chip level translation so any-format CMOS/LVDS/LVPECL inputs can be conditioned to LVPECL output levels without external bias networks. This minimizes cross-talk and provides superior supply-noise rejection, simplifying low-jitter clock distribution in electrically noisy backplanes.
Typical applications include redundant reference clock distribution in telecom equipment, 1G/10G Ethernet switch line cards, server backplane clock trees, FPGA/SoC reference clock fanout, and ATE or instrumentation where glitchless input switchover is mandatory. Independent OE pins per output bank let unused banks power down for additional energy savings.
When designing with the SI53323-B-GM, follow the datasheet reference schematic for the 16-QFN land pattern: route both LVPECL output pairs as 100 ohm differential microstrip with matched lengths, place the VDD decoupling network within 2 mm of the exposed pad, and tie the EP to a solid ground plane with multiple thermal vias. Always honor the datasheet AC-coupling requirement between LVPECL outputs and the next stage.
This page synthesizes distributor pricing, drop-in alternatives and practical layout notes not consolidated on any single distributor page.
ドロップイン代替品: SI53323-B-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI53323-B-GM （同一形状・フットプリント） — 相違点: Function, Number of Outputs, Operating Temperature, Output Type, Package.
クイック比較ツール — 並列比較する代替部品を選択:
SI53322-B-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI53323-B-GMR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI53344-B-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5338B-B-GMR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
PI6C557-03AQE
✅ ドロップイン✓ 在庫あり
$0.74 / 個
データシートを見る →SI53323-B-GM 仕様
| 機能 | Clock Fanout Buffer with Multiplexer |
| 出力数 | 4 |
| Number of Inputs | 2 (2:1 mux, any-format) |
| 出力タイプ | LVPECL |
| Input Type | Any-format (CMOS/LVDS/LVPECL/HCSL) |
| Maximum Output Frequency | 1.25 GHz |
| Supply Voltage - Core (VDD) | 2.5 V or 3.3 V (typical) |
| Supply Voltage - Output Bank | 2.5 V or 3.3 V (independent of core) |
| Output Enable | Yes (per bank) |
| Glitchless Mux Switching | Yes |
| パッケージ | 16-pin QFN (3x3 mm) with Exposed Pad |
| 動作温度 | -40C to +85C |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| MSLレベル | MSL1 (per JEDEC J-STD-020) |
SI53323-B-GM ピン構成
| ピン 1 | CLK0A — Differential clock input A, positive |
| ピン 2 | CLK0B — Differential clock input A, negative |
| ピン 3 | CLK1A — Differential clock input B, positive |
| ピン 4 | CLK1B — Differential clock input B, negative |
| ピン 5 | IN_SEL — Input select (0 = input A, 1 = input B) |
| ピン 6 | OE — Output enable (active high, per bank) |
| ピン 7 | VDD — Core supply (2.5 V or 3.3 V) |
| ピン 8 | GND — Ground |
| ピン 9 | Q0A — LVPECL output 0, positive |
| ピン 10 | Q0B — LVPECL output 0, negative |
| ピン 11 | Q1A — LVPECL output 1, positive |
| ピン 12 | Q1B — LVPECL output 1, negative |
| ピン 13 | Q2A — LVPECL output 2, positive |
| ピン 14 | Q2B — LVPECL output 2, negative |
| ピン 15 | Q3A — LVPECL output 3, positive |
| ピン 16 | Q3B — LVPECL output 3, negative |
| ピン EP | ePAD — Exposed thermal pad, must be soldered to GND |
主な用途
SI53323-B-GM の用途: 6 件s: Redundant Telecom Reference Clock Distribution, 10G/40G Ethernet Switch Line Cards, FPGA / SoC Reference Clock Fanout, ATE / Instrumentation Clock Trees, Server / Storage Backplane Clock Distribution, Industrial Control / Factory Automation.
Redundant Telecom Reference Clock Distribution
The SI53323-B-GM is purpose-built for redundant telecom reference clocking: its 2:1 any-format input mux performs glitchless switchover between a primary and backup reference, eliminating runt pulses on the LVPECL outputs that would otherwise corrupt downstream PHYs. The 1.25 GHz ceiling comfortably covers 156.25 MHz, 312.5 MHz and 625 MHz references used in OTN, SONET/SDH and 5G framer designs. Independent VDD core and output-bank supplies allow direct interface to 2.5 V PHYs without external level translators, simplifying BOM and improving jitter.
おすすめ
10G/40G Ethernet Switch Line Cards
On Ethernet switch line cards, the SI53323-B-GM fans out a single low-jitter 156.25 MHz or 625 MHz reference to multiple 10G/40G PHY or MAC ASICs with deterministic LVPECL skew. According to the Skyworks datasheet, the device's low additive jitter preserves the PHY's TX jitter budget and its glitchless 2:1 mux enables hitless failover between primary and backup system clocks. Per-bank output enable lets unused outputs power down for additional energy savings on partially populated line cards.
おすすめ
FPGA / SoC Reference Clock Fanout
FPGA and SoC designs often require one low-jitter reference to drive multiple GT/SerDes channels or PLL inputs across the board. The SI53323-B-GM delivers 4 differential LVPECL copies of the selected reference with sub-picosecond additive jitter, preserving link BER margin in PCIe Gen3/4, SATA, USB 3.x and SFP+ applications. The 16-pin 3x3 mm QFN with exposed pad keeps the fanout small enough to place near the FPGA, and Skyworks' independent output-bank supply enables level translation to 2.5 V or 3.3 V FPGA banks without external bias networks.
おすすめ
ATE / Instrumentation Clock Trees
In automatic test equipment (ATE) and bench instrumentation, the SI53323-B-GM distributes a single ultra-low-jitter reference to multiple ADC, DAC or digitizer channels. The glitchless 2:1 mux is critical during reference substitution or ATE calibration, where any runt pulse on the clock would propagate into the measurement. According to Skyworks datasheet, the device's CMOS core technology gives low propagation-delay variability across process and temperature - essential for deterministic sampling across channels.
おすすめ
Server / Storage Backplane Clock Distribution
Hyperscale servers and storage arrays use the SI53323-B-GM to fan a board-level reference to multiple CPU sockets, NVMe controllers and re-timer ICs with low deterministic skew. Independent core and output-bank supplies ease mixed-voltage designs where 2.5 V PHYs and 3.3 V re-timers coexist on the same board. The small 16-QFN (3x3 mm) and Skyworks' documented thermal performance also suit the dense backplane environment where airflow is constrained.
おすすめ
Industrial Control / Factory Automation
In industrial control and factory-automation backplanes, the SI53323-B-GM distributes a single fault-tolerant reference clock across PLCs, motion controllers and fieldbus gateways. Its industrial -40C to +85C temperature rating, RoHS compliance and any-format input support (LVDS, LVPECL, HCSL, CMOS) make it drop-in compatible with most motion-control and EtherCAT reference-clock architectures. The glitchless 2:1 input mux provides hitless redundancy between the primary controller clock and a hot-standby reference.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI53323-B-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI53322-B-GM | SI53323-B-GMR | SI53344-B-GM | PI6C557-03AQE |
|---|---|---|---|---|---|
| Package | 16-QFN (3x3 mm) EP | 16-QFN (3x3 mm) EP - same | 16-QFN (3x3 mm) EP - same | 16-QFN (3x3 mm) EP - same | 16-QFN (3x3 mm) EP - same |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Diodes Incorporated |
| Function | 2:4 LVPECL fanout + 2:1 mux | 1:4 LVPECL fanout (no mux) | 2:4 LVPECL fanout + 2:1 mux (identical die) | 2:4 LVPECL fanout (no mux) | LVPECL fanout buffer |
| Glitchless Mux | Yes (2:1) | No | Yes (2:1) | No | No |
| Input Format | Any-format (CMOS/LVDS/LVPECL/HCSL) | Any-format | Any-format | Any-format | LVPECL/LVDS/HCSL |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Integrated glitchless 2:1 input multiplexer in same 16-QFN package （vs SI53322-B-GM)
- Independent VDD core and VDDO output-bank supplies （vs PI6C557-03AQE)
- DC-to-1.25 GHz operation in a 3x3 mm QFN （vs SI5338B-B-GMR)
設計ノート
The Si53323-B-GM uses a 16-pin QFN with an exposed thermal pad (ePAD) that MUST be soldered to a clean, low-impedance ground plane using multiple thermal vias. Skyworks' reference layout recommends at least 4 vias in the ePAD to provide a low-inductance ground return for the LVPECL outputs. A floating or partially soldered ePAD will degrade jitter and may cause output instability.
Route each LVPECL differential pair (Q0A/Q0B, Q1A/Q1B, Q2A/Q2B, Q3A/Q3B) as a 100 ohm differential microstrip with matched trace lengths (skew less than 5 mil between P and N within a pair). AC-couple each output pair to the next stage per the Skyworks reference schematic - do NOT drive LVPECL DC-coupled into a 50 ohm to VCC-2V termination, as this violates the Si53323-B-GM output common-mode range.
The Si53323-B-GM has independent VDD (core) and VDDO (output-bank) supply pins. Per Skyworks datasheet, both should be bypassed with a 0.1 uF X7R ceramic placed within 2 mm of the respective supply pin, plus a bulk 10 uF tantalum or ceramic near the IC. Power the core and output bank from clean, low-noise LDO rails (do NOT share a noisy switching converter node) - the device's low additive jitter is only realized with low-ripple supplies.
Do not leave the IN_SEL pin floating - tie it high or low through a 10 kohm resistor. A floating IN_SEL can cause the input mux to oscillate, producing runt pulses on the LVPECL outputs. Also, the OE pin is per-bank and active high; an unused bank should be tied low to reduce dynamic current. Verify all unused input pins (e.g. CLK1A/B when only CLK0 is used) are tied to a defined logic level, not left floating.
コンプライアンス情報
RoHS compliant per Skyworks product page. Not AEC-Q100 qualified - this is a commercial/industrial timing IC. MSL1 per JEDEC J-STD-020 simplifies board assembly. Pb-free reflow profile per JEDEC J-STD-020.
