W55RP20 - RP2040+W5500 Ethernet SiP MCU | WIZnet
部品番号: W55RP20 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $3.05 | $3.05 |
| 10 | $2.9 | $29.00 |
| 100 | $2.75 | $275.00 |
| 500 | $2.6 | $1,300.00 |
| 1,000 | $2.45 | $2,450.00 |
W55RP20 概要
A System-in-Package device stacks or side-by-side mounts two dies within a single molded package, so the W55RP20 functions electrically as one microcontroller with built-in Ethernet, eliminating the two-chip RP2040-plus-W5500 solution that previously required separate routing, crystals, and power domains. In the product hierarchy it sits as: ioMCU -> communications controller microcontroller -> Ethernet microcontroller -> IoT connectivity IC.
Key features include the dual Cortex-M0+ cores at 133 MHz, 2 MB flash for code storage, 264 kB SRAM in six independent banks, and the W5500 subsystem with a hardwired TCP/IP stack supporting 8 hardware sockets, which offloads protocol processing entirely from the CPU. A 12-channel DMA controller supports memory-to-peripheral, peripheral-to-memory, and memory-to-memory transfers, each channel with its own control and status registers, letting the processor switch to other tasks or low-power states during large data transfers.
The W5500 die provides a hardware TCP/IP stack implementing MAC and PHY functionality for 10/100 Mbps Ethernet, so networking is deterministic and does not consume MCU cycles for protocol handling. This architecture suits applications where wire-speed throughput and low jitter matter more than a large software network stack.
Typical applications include industrial IoT gateways, networked sensor nodes, smart-building controllers, and Ethernet-enabled embedded systems where developers want Raspberry Pi Pico-class processing plus native wired networking in one chip.
Design consideration: as a SiP, thermal dissipation is combined from both dies; verify total power budget and provide adequate ground-plane copper under the exposed pad for heat spreading and signal return.
This page synthesizes distributor pricing, availability, evaluation-board references, and practical design notes not consolidated in the manufacturer datasheet.
ドロップイン代替品: W55RP20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: W55RP20 （同一形状・フットプリント） — 相違点: Product Type, SRAM.
クイック比較ツール — 並列比較する代替部品を選択:
W55RP20-S2E
✅ ドロップイン✓ 在庫あり
$3.05 / 個
データシートを見る →W55RP20 最大定格＆電気的特性
| Core | Dual Arm Cortex-M0+ |
| Core Clock Frequency | 133 MHz |
| Flash Memory | 2 MB on-chip |
| SRAM | 264 kB on-chip in six independent banks |
| Ethernet Controller | W5500 with hardwired TCP/IP stack |
| Ethernet Speed | 10/100 Mbps |
| Hardware Sockets | 8 |
| DMA Channels | 12 independent channels |
| DMA Transfer Types | Memory-to-peripheral, peripheral-to-memory, memory-to-memory |
| パッケージ | 68-VFQFN Exposed Pad |
| 実装タイプ | Surface Mount |
| Product Type | SiP ioMCU / Communications Controller MCU |
| Integrated Dies | RP2040 MCU + W5500 Ethernet controller |
W55RP20 68-vfqfn exposed pad ピン配置ガイド
W55RP20 (68-vfqfn exposed pad パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: W55RP20.
詳細は データシート をご参照ください。
主な用途
W55RP20 の用途: 6 件s: Industrial IoT Gateways, Networked Sensor Nodes, Smart Building Controllers, Embedded Ethernet Adapters / Serial-to-Ethernet Bridges, Networked Consumer and Smart Home Devices, Test, Measurement, and Networking Equipment.
Industrial IoT Gateways
The W55RP20 fits industrial IoT gateway roles because its W5500 die provides a hardwired TCP/IP stack with 8 hardware sockets at 10/100 Mbps, delivering deterministic network throughput without consuming CPU cycles on protocol handling. The dual Cortex-M0+ cores at 133 MHz run protocol conversion logic (Modbus-to-MQTT, serial-to-Ethernet) while the 2 MB flash and 264 kB SRAM accommodate buffer-heavy applications. The 12-channel DMA streams sensor data to Ethernet socket buffers in the background, keeping both cores free for real-time control tasks. Compared to a software network stack, the hardware stack reduces jitter, an important factor in factory automation polling cycles. The Raspberry Pi-WIZnet industrial case study specifically highlights SiP adoption in smart factory deployments.
おすすめ
Networked Sensor Nodes
For Ethernet-connected sensor nodes, the W55RP20 consolidates MCU, flash, and PHY into one 68-VFQFN device, shrinking node BOM count and board area versus a two-chip RP2040 plus W5500 layout. The hardware TCP/IP stack supports persistent connections to SCADA or cloud brokers across 8 sockets, so a single node can publish to redundant endpoints simultaneously. The 12-channel DMA moves ADC and peripheral data into W5500 TX buffers memory-to-peripheral style, allowing the Cortex-M0+ cores to sleep between samples and extending power budget in duty-cycled deployments. With 2 MB on-chip flash, nodes can store local logging code and firmware-update images. The SiP's integrated PHY removes external magnetics layout sensitivity common to discrete PHY designs.
おすすめ
Smart Building Controllers
Smart-building controllers benefit from the W55RP20's combination of dual-core processing and native wired Ethernet for BMS integration. The W5500 die's 8 hardware sockets allow simultaneous communication with multiple building subsystems - lighting, HVAC, and access control - over separate TCP connections with no software stack maintenance. The 264 kB SRAM in six independent banks supports concurrent sensor aggregation and network buffering, while the 133 MHz dual Cortex-M0+ cores partition control loops from communication handlers. Because the hardwired TCP/IP stack is deterministic, scheduled control actions are not delayed by network stack processing. The 2 MB flash accommodates OTA-update-capable firmware images with a safe rollback partition, a common requirement in installed building infrastructure.
おすすめ
Embedded Ethernet Adapters / Serial-to-Ethernet Bridges
The W55RP20 is the silicon behind WIZnet's W55RP20-S2E serial-to-Ethernet variant, making it a natural choice for general-purpose UART/TCP bridge products. The dual Cortex-M0+ cores split work cleanly: one core services UART traffic with DMA-supported transfers through the 12-channel DMA controller, while the other manages W5500 socket buffers, achieving transparent bidirectional bridging at line rate. The hardwired TCP/IP stack guarantees consistent packet turnaround for legacy industrial equipment expecting serial-tunnel behavior. With 2 MB flash, vendors can embed configuration web servers, multiple firmware profiles, and TLS-light protocols. Developers can validate designs on the W55RP20-EVB-Pico, which is supported in mainline Zephyr for portable bridge firmware.
おすすめ
Networked Consumer and Smart Home Devices
Consumer connected devices - printers, networked appliances, and smart home hubs - use the W55RP20 to add wired Ethernet with minimal engineering risk. The W5500 die has shipped in millions of WIZnet Ethernet ICs, so its TCP/IP offload behavior is well understood, while the RP2040 die inherits the extensive Raspberry Pi Pico software ecosystem including MicroPython, C/C++ SDK, and community libraries. This combination shortens development cycles: networking is configuration rather than stack development. The 133 MHz dual cores run UI, motor, or audio tasks alongside networking, and 264 kB SRAM handles JSON parsing and TLS session data for cloud connectivity. Wired Ethernet in consumer devices also avoids Wi-Fi certification cost for the network path.
おすすめ
Test, Measurement, and Networking Equipment
In bench instruments and networked test equipment, the W55RP20 provides a deterministic data path: the W5500 hardware TCP/IP stack streams measurement results over Ethernet with low, consistent latency, while the 12-channel DMA controller pipelines ADC sample blocks into socket buffers without core intervention - the datasheet explicitly notes the DMA lets the processor switch to other tasks or low-power states during large transfers. The dual Cortex-M0+ cores separate acquisition control from user-interface and command parsing, and 2 MB flash stores calibration tables and multiple instrument personalities. The exposed-pad 68-VFQFN package supports the ground-plane integrity needed in mixed-signal instrument layouts, and the SiP form factor simplifies EMI enclosure design versus two separate networked dies.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: W55RP20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | W55RP20-S2E |
|---|---|---|
| Package | 68-VFQFN Exposed Pad | 68-VFQFN Exposed Pad - same |
| Brand | WIZnet | WIZnet |
| Core | Dual Arm Cortex-M0+ @ 133 MHz | Dual Arm Cortex-M0+ @ 133 MHz |
| Flash Memory | 2 MB on-chip | 2 MB on-chip |
| SRAM | 264 kB (six banks) | 264 kB (six banks) |
| Ethernet Controller | W5500 hardwired TCP/IP, 8 sockets | W5500 hardwired TCP/IP, 8 sockets |
| DMA Channels | 12 | 12 |
| Pre-loaded Firmware | None (user-programmable) | Serial-to-Ethernet (S2E) firmware |
主な差別化要因
- Single-package consolidation of MCU and Ethernet （vs RP2040 + W5500 two-chip solution)
- S2E variant ships with ready-made firmware （vs W55RP20-S2E)
- Hardware TCP/IP offload versus software stacks （vs MCUs with software IP stacks (e.g., generic Cortex-M0+ MCUs))
設計ノート
The W55RP20 is a dual-die SiP (RP2040 + W5500) in a 68-VFQFN exposed-pad package, so the exposed pad must be soldered to a solid ground pour for both thermal dissipation and signal return of the Ethernet PHY section. Follow the W55RP20-EVB-Pico reference layout from the WIZnet GitHub repository, including the W5500-side magnetics placement and Bob Smith termination circuit. Keep the 25 MHz Ethernet crystal traces short and guarded by ground, and place decoupling capacitors for both die power domains close to their respective supply pins.
Because two dies share one package, budget the combined power: the RP2040 cores at 133 MHz plus the W5500 PHY in active 100 Mbps mode draw current from the same supply rails through the SiP. Estimated: verify total load against your regulator headroom using RP2040 and W5500 datasheet current figures, since the W55RP20 datasheet may specify them per die. Add bulk capacitance (at least 10 uF) near the SiP in addition to per-pin decoupling, and sequence power-up per the WIZnet datasheet requirements to avoid PHY latch-up.
Do not treat the W55RP20 as a pin-compatible drop-in for either the RP2040 (QFN-56) or the standalone W5500 (QFN-48); it is a distinct 68-pin footprint requiring its own land pattern. Also, developers migrating from the two-chip W5500-EVB-Pico must note the community-documented distinction (Raspberry Pi forums): the W55RP20-EVB-Pico is a single-chip design without the LDO/PoE configuration of the older board. When using the S2E variant, remember it ships with factory firmware - reflashing replaces that firmware permanently.
コンプライアンス情報
Compliance data not present in the provided web data; consult the official WIZnet product page and datasheet for RoHS/REACH declarations.
