FPGA & CPLD

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XCZU9EG-2FFVB1156I - Zynq UltraScale+ MPSoC EG | AMD
XCZU9EG-2FFVB1156I

XCZU9EG-2FFVB1156I - Zynq UltraScale+ MPSoC EG | AMD

The AMD XCZU9EG-2FFVB1156I is a Zynq UltraScale+ MPSoC EG family device, combining a quad-core ARM Cortex-A53 application processor, dual-core ARM Cortex-R5 real-time processor, ARM Mali-400 MP2 graphics processing unit, and 599,550 programmable logic cells in a single 1156-pin FCBGA package. This System-on-Chip (SoC) integrates the processing system (PS) and programmable logic (PL) on one die, enabling heterogeneous computing for demanding embedded applications. A Zynq UltraScale+ MPSoC is a class of adaptive SoC that pairs multi-core ARM processing with FPGA fabric. The EG variant targets embedded and industrial applications, offering a balance of processing performance, programmable logic capacity, and I/O flexibility. It sits within the broader hierarchy: Zynq UltraScale+ MPSoC -> adaptive SoC -> System-on-Chip -> semiconductor device. Key features include 599,550 logic cells, 32.1 Mb of block RAM, 1,968 DSP slices, and support for 533 MHz (Cortex-R5), 600 MHz (Mali-400), and 1.3 GHz (Cortex-A53) clock speeds. The device operates at 0.85V core voltage and is fabricated on a 20nm process. The -2 speed grade offers a balance of performance and power efficiency. The architecture integrates the PS with the PL via high-bandwidth AXI interfaces, enabling low-latency data movement between software and hardware accelerators. The Mali-400 MP2 GPU supports 2D/3D graphics, while the video codec unit handles H.264/H.265 encoding and decoding. The device includes comprehensive security features such as RSA authentication, AES decryption, and secure boot. Typical applications include software-defined radio, industrial motor control, medical imaging, aerospace and defense systems, and multi-axis robotics. The combination of real-time processing (Cortex-R5), application processing (Cortex-A53), and programmable logic makes it suitable for complex control and signal processing tasks. When designing with this device, careful attention must be paid to power supply sequencing, decoupling, and thermal management. The 1156-pin FCBGA package requires a multi-layer PCB with controlled impedance for high-speed transceivers and DDR memory interfaces.

USD $11,800.00 재고 있음
XCZU9EG-2FFVC900E - Zynq UltraScale+ MPSoC EG | AMD
XCZU9EG-2FFVC900E

XCZU9EG-2FFVC900E - Zynq UltraScale+ MPSoC EG | AMD

The AMD XCZU9EG-2FFVC900E is a Zynq UltraScale+ MPSoC EG family device, integrating a quad-core ARM Cortex-A53 application processor, dual-core ARM Cortex-R5 real-time processor, and ARM Mali-400 MP2 graphics processing unit with programmable logic. It is housed in a 900-ball FCBGA package (31x31 mm) and is designed for high-performance embedded applications requiring both processing and FPGA flexibility. A System-on-Chip (SoC) FPGA combines a hard processor system (PS) with programmable logic (PL) on a single die, enabling software and hardware co-design. The Zynq UltraScale+ MPSoC family extends this concept with heterogeneous processing, including real-time and graphics cores, making it suitable for advanced driver assistance systems (ADAS), industrial automation, and aerospace applications. Key features include 599K+ logic cells, 533 MHz for the Cortex-A53, 600 MHz for the Cortex-R5, and 1.3 GHz for the Mali-400 MP2. The device supports DDR4, LPDDR4, and 32-bit/64-bit memory interfaces, and includes high-speed transceivers for serial connectivity. The EG variant provides a balanced mix of logic and DSP resources, with 2,520 DSP slices and 32.1 Mb of block RAM. The architecture leverages TSMC 16nm FinFET process technology, offering high performance with low power consumption. The programmable logic is based on the UltraScale+ architecture, featuring enhanced routing, clocking, and I/O capabilities. The device supports partial reconfiguration, enabling dynamic updates to the PL while the PS continues operation. Typical applications include 5G wireless baseband processing, machine vision systems, medical imaging, and defense electronics. The combination of ARM cores and FPGA fabric allows for real-time signal processing, hardware acceleration, and flexible I/O interfacing. When designing with this device, careful attention must be paid to power supply sequencing, decoupling, and thermal management. The 900-ball FCBGA package requires a multi-layer PCB with controlled impedance for high-speed signals. AMD provides comprehensive design resources, including the Zynq UltraScale+ MPSoC data sheet (DS891) and pinout files.

USD $3,600.00 재고 있음
iCE40LP384-SG48 - 384 LUT Ultra-Low-Power FPGA | Lattice Semi
iCE40LP384-SG48

iCE40LP384-SG48 - 384 LUT Ultra-Low-Power FPGA | Lattice Semi

The Lattice Semiconductor iCE40LP384-SG48 is an ultra-low-power Field Programmable Gate Array (FPGA) from the iCE40 LP family, delivering 384 Look-Up Tables (LUTs) in a 48-pin QFN (SG48) package with 1.2V core voltage and 21 user I/O. It is fabricated on a 40 nm CMOS process optimized for minimal static and dynamic power consumption, targeting mobile, handheld, and energy-harvesting designs where battery life dominates the bill of materials. The device integrates a hardened I2C core, SPI configuration interface, and on-chip PLL blocks, providing a complete glue-logic platform in a sub-1 mW active power envelope. An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks (LUTs), programmable interconnect, and I/O cells that can be re-programmed to implement arbitrary digital logic. Low-power FPGAs such as the iCE40 LP family occupy a unique tier in the programmable logic hierarchy - sitting above fixed-function ASICs (which offer zero flexibility) and below high-density FPGAs from Xilinx and Intel (which offer millions of LUTs at the cost of watts). The iCE40 LP family is the de-facto choice when an application needs custom logic, multiple interfaces, or hardware acceleration, but the system can only afford a few hundred microwatts of quiescent draw. Within the Lattice portfolio, iCE40LP sits between the older iCE65 and the higher-density ECP5 family. Key features include 384 4-input LUTs, 21 user I/O pins, embedded RAM (4 kbits block RAM equivalent), two 16-bit timers/counters, two I2C controllers, one SPI controller, and a hard PLL supporting clock multiplication. The device operates from a 1.14 V to 1.26 V core supply with separate I/O bank supplies from 1.71 V to 3.465 V, enabling direct interfacing to 1.8 V, 2.5 V, and 3.3 V peripherals. Typical static current is below 100 uA at 25 C, and active current scales linearly with toggle rate and logic utilization. Architecturally, the iCE40LP384 uses a non-volatile SRAM configuration cell (volatile SRAM, but loaded from NV memory at boot) backed by NVCM or SPI Flash. Logic is implemented as 4-input LUTs feeding a programmable interconnect fabric, with carry chains for arithmetic and block RAM for storage. The hard I2C and SPI controllers reduce LUT usage for common bus interfaces, leaving more logic free for application-specific state machines and datapaths. Typical applications include mobile device glue logic, IoT sensor hubs, wearable sensor aggregation, low-power display controllers (SPI/parallel LCD), handheld medical peripherals, and battery-powered industrial sensor nodes. The 48-pin QFN package balances I/O count with hand-solder-friendly footprint for prototype work. When designing with this device, remember that the 1.2 V core rail must be sequenced within 50 ms of the I/O rails to prevent I/O cell back-powering through ESD diodes. Use the Lattice iCEcube2 design suite for synthesis, place-and-route, and bitstream generation.

USD $2.10 재고 있음
iCE40UP5K-SG48 - 5280 LUT UltraPlus FPGA QFN-48 | Lattice
iCE40UP5K-SG48

iCE40UP5K-SG48 - 5280 LUT UltraPlus FPGA QFN-48 | Lattice

The Lattice Semiconductor iCE40UP5K-SG48 is an iCE40 UltraPlus low-power FPGA with 5280 Look-Up Tables (LUTs), 128 Kbit of dual-port block RAM, 1 Mbit of single-port RAM, and eight 16x16 DSP MAC blocks, housed in a 48-pin VFQFN exposed-pad (SG48) package. A Field Programmable Gate Array (FPGA) is a reconfigurable logic device that implements digital circuits through programmable interconnect and logic blocks. Within the semiconductor hierarchy, FPGAs sit alongside microcontrollers and ASICs as programmable silicon; the iCE40 UltraPlus family occupies the ultra-low-power end of the FPGA spectrum, targeting mobile, IoT, and AI/ML edge applications where milliwatts matter. Key features include two hard-IP SPI and two hard-IP I2C controllers that offload protocol handling from soft logic, two internal oscillators (10 kHz and 48 MHz) that eliminate external clock sources in cost-sensitive designs, three 24 mA constant-current RGB outputs with hard RGB PWM IP for direct LED drive, and dedicated DSP blocks with 16x16 multiply and 32-bit accumulate for lightweight neural network inference. Architecturally, the iCE40UP5K combines a 4-input LUT plus carry chain plus flip-flop fabric with 120 Kbit of distributed sysMEM block RAM and 1 Mbit SPRAM, a phase-locked loop (PLL) for clock synthesis, and low-power 1.2V core operation consistent with the family's positioning as the lowest-power machine learning solution in its class. Typical applications include sensor aggregation and pre-processing for mobile platforms, always-on AI/ML inference at the edge, and system management or bridge logic where two SPI and two I2C hard IPs reduce firmware complexity. The SG48 QFN footprint also suits compact boards such as the iCEBreaker open-source FPGA platform. Design consideration: use the SG48 package with QSPI flash configuration and account for the exposed thermal pad in PCB layout for reliable ground return. This page synthesizes distributor listings, drop-in family alternatives, and practical design notes not consolidated in the manufacturer datasheet.

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