5CSEBA2U19C7N vs 5CSEBA2U23A7N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci 5CSEBA2U19C7N disebabkan oleh Intel dan 5CSEBA2U23A7N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
5CSEBA2U19C7N - Cyclone V SE SoC FPGA, 25K LE, Dual ARM Cortex-A9 | Intel
5CSEBA2U19C7N ✓ AktifPengandingan Spesifikasi
| Parametr | 5CSEBA2U19C7N | 5CSEBA2U23A7N |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 25,000 LE | 25,000 LE |
| Adaptive Logic Modules (ALMs) | 9,430 ALM | — |
| ALUTs | 9,430 | — |
| DSP Blocks | 66 (variable-precision 18x18) | Variable-precision DSP (count [DATA_NEEDED: exact count]) |
| Embedded Memory | 1,400 Kbits (M9K + MLAB) | M10K blocks (count [DATA_NEEDED: exact M10K/M20K count]) |
| HPS Processor | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Clock Frequency | 925 MHz | — |
| L1 Cache (per core) | 32 KB I-cache + 32 KB D-cache | — |
| L2 Cache | 512 KB shared | — |
| User I/O Pins | [DATA_NEEDED: exact user I/O count] | — |
| Kemasan | 484-pin UBGA (19x19 mm, 1.0 mm pitch) | 672-UBGA (23x23 mm) |
| Speed Grade | C7 | 7 |
| Suhu Operasi | Commercial / Industrial (TJ from data) | — |
| Process Technology | TSMC 28 nm low-power | 28 nm low-power |
| Jenis Pemasangan | Surface Mount (BGA) | Surface Mount (BGA) |
| Aras MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Status RoHS | Compliant | Compliant (per ampheo listing) |
| MPN Code | — | 5CSEBA2U23A7N (Cyclone V SE A2, U23 package) |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 700 MHz |
| User I/O | — | 188 |
| Temperature Grade | — | A (Commercial, 0C to +85C) [DATA_NEEDED: exact junction range] |
| Operating Voltage (Core) | — | 1.1 V (typical FPGA core, multi-rail HPS) |
| Configuration Scheme | — | HPS-boot of FPGA fabric via configuration QSPI |
| PLLs | — | Fractional PLLs (count [DATA_NEEDED: exact PLL count]) |