CDK2307AILP64 vs CDK2307DILP64 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci CDK2307AILP64 disebabkan oleh Cadeka dan CDK2307DILP64 disebabkan oleh MaxLinear. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | CDK2307AILP64 | CDK2307DILP64 |
|---|---|---|
| Merek | Cadeka | MaxLinear |
| Kategori | ADC/DAC | ADC/DAC |
| Status Lingkungan Hidup | Aktif | Aktif |
| Manufacturer | Cadeka Microcircuits (MaxLinear) | Cadeka Microcircuits (now MaxLinear) |
| Part Number | CDK2307AILP64 | — |
| Description | Dual 12/13-bit 20/40/65/80 MSPS Analog-to-Digital Converter | — |
| Pemecahkatan | 13 bit (12-bit option via CDK2308 family) | 12-bit / 13-bit (user selectable) |
| Sampling Rate (this variant) | 20 MSPS | — |
| Sampling Rate (family max) | 80 MSPS (CDK2307AILP64 = 20 MSPS grade) | — |
| Number of Channels | 2 (dual, simultaneous sampling) | 2 (dual) |
| Input Type | Single-ended analog input | Single-Ended |
| Output Interface | Parallel CMOS | Parallel CMOS |
| Core Supply Voltage | 1.8 V | — |
| I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Power Dissipation | 30 mW at 20 MSPS; 55/85/102 mW at 40/65/80 MSPS | — |
| Reference | Internal (bandgap, integrated) | Internal bandgap (external REFIN supported) |
| Kemasan | 64-pin QFN (LP64) with exposed pad, 9x9 mm | QFN-64 (7 mm x 7 mm) with exposed pad |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | -40C to +85C (industrial) [DATA_NEEDED: exact temp grade] | [DATA_NEEDED: operating temperature range] |
| Pin Compatibility | Pin-compatible with CDK2308 family (12-bit variant) | — |
| Status RoHS | Compliant | Compliant (per distributor listings) |
| Fungsi | — | Dual Analog-to-Digital Converter |
| kadar sampling | — | 20 / 40 / 65 / 80 MSPS (family-wide) |
| Analog Supply Voltage | — | 1.7 V to 3.6 V |
| Digital Supply Voltage | — | 1.7 V to 3.6 V |
| Power Consumption | — | 102 mW per channel at 80 MSPS |
| Architecture | — | Pipelined with digital error correction |