EP1810GM883 vs EP1810LC-20T Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810GM883 disebabkan oleh Altera dan EP1810LC-20T disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1810GM883 EP1810LC-20T
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Classic EPLD (EP1810 series) Altera Classic EPLD
Device Type UV-Erasable Programmable Logic Device (EPLD) —
Macrocells 48 48
Dedicated Inputs 12 —
User I/O Pins 48 —
Total Terminals 68 —
Global Clocks 4 —
Supply Voltage (Vcc) 4.5 V to 5.5 V (nominal 5 V) —
Propagation Delay (tpd) 45 ns (max) —
Maximum Toggle Frequency (fmax) [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] —
Process Technology CMOS, UV-erasable —
Kemasan 68-Pin Ceramic Pin Grid Array (PGA) —
Suhu Operasi -55C to +125C (MIL-STD-883 Class B) 0C to +70C (commercial)
Screening MIL-STD-883 Class B (suffix '883' denotes MIL processing) —
Jenis Pemasangan Through-Hole (PGA socket) Surface Mount (socket-compatible)
Status RoHS [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] Non-compliant (legacy 5V PLCC)
Lead-Free [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] —
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 900 gates
Logic Array Blocks (LABs) — 4 x 12 macrocells
Maximum Toggle Frequency — 50 MHz
Pin-to-Pin Logic Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5 V
Package Type — PLCC-68 (J-lead)
Configuration Memory — On-chip EEPROM (non-volatile)
Programming Interface — JTAG (IEEE 1149.1) and Altera Master/Slave serial
Shipping Format — Tape & Reel ("T" suffix)

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