EP1810JC-45 vs EP1810JI-45 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JC-45 disebabkan oleh Altera dan EP1810JI-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810JC-45 | EP1810JI-45 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Frekuensi Klock Maksimum | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Maximum Supply Voltage | 5.25 V | — |
| Kemasan | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| Kiraan Pin | 68 | — |
| Package Code | QCCJ | QCCJ |
| Temperature Grade | Commercial | INDUSTRIAL |
| Jenis Pemasangan | Surface Mount | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 50 ns |
| Configurable I/O Lines | — | 48 |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Suhu Operasi | — | -40 °C to +85 °C |
| Tegangan Pemberi Arus | — | 5 V (TTL compatible) |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |