EP1810JC35 vs EP1810GI-45 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JC35 disebabkan oleh Altera dan EP1810GI-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810JC35 | EP1810GI-45 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 48 | 24 |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | — |
| Frekuensi Klock Maksimum | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| Suhu Operasi | 0 C to +70 C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Kemasan | PLCC-68 (J-lead, ceramic) | — |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance for EP1810JC35] | Non-compliant (ceramic PGA) |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Speed Grade | — | -45 |
| Technology | — | CMOS |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| Kiraan Pin | — | 68 |
| Jenis Pemasangan | — | Through-Hole |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| Tegangan Pemberi Arus | — | [DATA_NEEDED: VCC range] |