EP1810LC-20 vs EP1810JI-45 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810LC-20 disebabkan oleh Intel dan EP1810JI-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810LC-20 | EP1810JI-45 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP Complex PLD |
| Usable Gates | 900 | — |
| Macrocells | 48 | — |
| Maximum Operating Frequency | 50 MHz | 33.3 MHz |
| Propagation Delay (tPD) | 20 ns | 50 ns |
| Tegangan Pemberi Arus | 5 V (4.75 V to 5.25 V) | 5 V (TTL compatible) |
| Technology | CMOS EPROM | CMOS EPROM |
| Programmability | UV-Erasable / OTP | — |
| Dedicated Inputs | 12 | 12 |
| Kemasan | 68-pin PLCC | — |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) | — |
| Speed Grade | 20 ns (commercial) | — |
| Suhu Operasi | 0C to +70C (commercial) | -40 °C to +85 °C |
| Jenis Pemasangan | Surface Mount | — |
| Status RoHS | [DATA_NEEDED: rohs status] | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Macrocell Count | — | 48 |
| Configurable I/O Lines | — | 48 |
| Package Code | — | QCCJ |
| Package Type | — | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |