EP1M350F780I5N vs EP1M350F780C6N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1M350F780I5N disebabkan oleh Altera dan EP1M350F780C6N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP1M350F780I5N | EP1M350F780C6N |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Family | Mercury PLD | Mercury (EP1M350) |
| Manufacturer | Altera (now Intel) | — |
| Typical Gates | 350,000 | — |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Core Voltage | 1.5 V | — |
| I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Kemasan | 780-pin FBGA (FineLine BGA) | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Process Technology | 0.15 um CMOS | — |
| Configuration Memory | SRAM-based | — |
| Operating Temperature Grade | Industrial -40C to +85C | — |
| Speed Grade | 5 | — |
| High-Speed Transceivers | Embedded (per Mercury family) | — |
| PLLs | Dedicated (per Mercury family) | — |
| Embedded Memory | Dual-port RAM blocks | — |
| Lead-Free / RoHS | Yes (per 'N' suffix) | — |
| Design Software | Altera Quartus II | — |
| Programming Interface | JTAG / Passive Serial | — |
| Device Type | — | Loadable Programmable Logic Device (PLD) / FPGA |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| Suhu Operasi | — | 0 C to 85 C |
| Configuration Interface | — | JTAG (IEEE 1149.1) / passive serial |
| Status RoHS | — | [DATA_NEEDED: rohs_status] |
| Aras MSL | — | [DATA_NEEDED: msl_level] |
| Lead-Free | — | [DATA_NEEDED: lead_free] |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |