EP1M350F780I5N vs EP1M350F780I5 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1M350F780I5N disebabkan oleh Altera dan EP1M350F780I5 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndPengandingan Spesifikasi
| Parametr | EP1M350F780I5N | EP1M350F780I5 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | Mercury PLD | — |
| Manufacturer | Altera (now Intel) | — |
| Typical Gates | 350,000 | — |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Core Voltage | 1.5 V | — |
| I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Kemasan | 780-pin FBGA (FineLine BGA) | 780-ball FineLine BGA (F780) |
| Process Technology | 0.15 um CMOS | — |
| Configuration Memory | SRAM-based | — |
| Operating Temperature Grade | Industrial -40C to +85C | — |
| Speed Grade | 5 | 5 |
| High-Speed Transceivers | Embedded (per Mercury family) | — |
| PLLs | Dedicated (per Mercury family) | — |
| Embedded Memory | Dual-port RAM blocks | — |
| Lead-Free / RoHS | Yes (per 'N' suffix) | — |
| Design Software | Altera Quartus II | — |
| Programming Interface | JTAG / Passive Serial | — |
| Device Family | — | Altera Mercury (EP1M) Enhanced Configuration Device |
| Fungsi | — | FPGA configuration PROM with integrated controller |
| Storage Density Code | — | 350 (high-density) |
| Supported Configuration Schemes | — | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | — | Configuration controller + flash memory array |
| Programming Method | — | In-system programmable via Altera Quartus / JTAG |
| Temperature Grade (suffix "I") | — | Industrial |
| Target FPGA Compatibility | — | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | — | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | — | Yes |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |