EP1SGX40FF1020C7 vs EP1S60F1020C7 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1SGX40FF1020C7 disebabkan oleh Altera dan EP1S60F1020C7 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP1SGX40FF1020C7 - Stratix GX FPGA 41,250 LE | Intel | 1020-BGA
EP1SGX40FF1020C7 ⚠ Bahagian terakhir untuk beli
Pengandingan Spesifikasi
| Parametr | EP1SGX40FF1020C7 | EP1S60F1020C7 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Series | Stratix GX | Stratix |
| Family | Stratix GX (EP1SGX40) | Stratix (EP1S60) |
| Logic Elements (LE) | 41,250 | — |
| Configurable Logic Blocks (CLB) | 4,125 | — |
| Embedded Memory (bits) | 3,423,744 | — |
| User I/O Pins | 624 | — |
| Number of Logic Array Blocks (LAB) | 4,125 | — |
| Number of I/O Banks | 12 | — |
| Core Supply Voltage (VCCINT) | 1.425 V to 1.575 V (nominal 1.5 V) | — |
| Speed Grade | 7 (-7, mid-speed) | 7 |
| Process Technology | CMOS | — |
| Suhu Operasi | 0 °C to 85 °C (commercial) | 0C to +85C (Commercial) |
| Kemasan | 1020-ball FC-FBGA (S-PBGA-B1020) | 1020-BBGA, FCBGA, 33 x 33 mm, 1.0 mm pitch |
| Package Dimensions | 33 mm × 33 mm | — |
| Ball Pitch | 1.00 mm | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | Compliant | Compliant (lead-free) |
| Configuration Modes | PS, PPS, PPA, JTAG, AS | — |
| DSP Blocks (9-bit) | 176 | — |
| Transceiver Channels | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps | — |
| PLLs | 8 enhanced + per-transceiver PLLs | Up to 12 enhanced PLLs per die |
| Logic Elements | — | 57,120 |
| Total Memory Bits | — | 5,215,104 |
| Maximum User I/O | — | 773 |
| Logic Family | — | CMOS |
| Core Supply Voltage | — | 1.5 V |
| Logic Cells / Logic Blocks | — | 6,570 (per datasheet Section I nomenclature) |
| DSP Blocks | — | Embedded dedicated multiplier / adder blocks |
| Configuration Method | — | Serial or parallel with optional decompression |
| Aras MSL | — | 3 (per BGA moisture-sensitivity norms) |