EP1SGX40FF1020I5 vs EP1SGX40FF1020C7 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1SGX40FF1020I5 disebabkan oleh Intel dan EP1SGX40FF1020C7 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP1SGX40FF1020C7 - Stratix GX FPGA 41,250 LE | Intel | 1020-BGA
EP1SGX40FF1020C7 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP1SGX40FF1020I5 | EP1SGX40FF1020C7 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Family | Stratix GX | Stratix GX (EP1SGX40) |
| Logic Elements (LEs) | 41,250 | — |
| Configurable Logic Blocks (CLBs) | 4,125 | — |
| Process Technology | 130 nm CMOS | CMOS |
| Configuration | SRAM-based LUT | — |
| Nominal Core Supply Voltage | 1.5 V | — |
| Kemasan | 1020-ball FineLine BGA (FF1020) | 1020-ball FC-FBGA (S-PBGA-B1020) |
| Terminal Pitch | 1.00 mm | — |
| Package Shape | Square | — |
| Suhu Operasi | -40C to +100C (Industrial) | 0 °C to 85 °C (commercial) |
| Speed Grade | I5 | 7 (-7, mid-speed) |
| Jenis Pemasangan | Surface Mount (BGA) | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Logic Family | CMOS | — |
| Hardened Transceivers | 3.125 Gbps multi-channel (per Stratix GX family) | — |
| Series | — | Stratix GX |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| Embedded Memory (bits) | — | 3,423,744 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Package Dimensions | — | 33 mm × 33 mm |
| Ball Pitch | — | 1.00 mm |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| Transceiver Channels | — | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |
| PLLs | — | 8 enhanced + per-transceiver PLLs |