EP20K100ETC144-2N vs EP20K100EFC144-1 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K100ETC144-2N disebabkan oleh Altera dan EP20K100EFC144-1 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP20K100ETC144-2N | EP20K100EFC144-1 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | NRND |
| Family | APEX-20KE | — |
| Device Type | FPGA (Field Programmable Gate Array) | FPGA (Field Programmable Gate Array) |
| Number of Logic Elements/Cells | 4160 | — |
| Number of LABs/CLBs | 416 | — |
| Total RAM Bits | 53248 | — |
| Number of Gates | 263000 (typical) | — |
| Number of User I/Os | 92 | — |
| Kemasan | 144-LQFP (TQFP, 20x20 mm, 0.5 mm pitch) | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Operating Supply Voltage (Core) | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Maximum Operating Frequency | 250 MHz | — |
| Propagation Delay | 1.6 ns | 1.6 ns |
| Process Technology | 0.22 µm all-layer copper-metal | 0.15-µm all-layer copper |
| Gambaran Suhu Operasi | 0 C to 85 C (TJ) | — |
| ESBs (Embedded System Blocks) | 4 | — |
| Programming Interface | JTAG (IEEE 1149.1) / FastON | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | APEX 20KE |
| Typical Gates | — | 100,000 |
| Maximum System Gates | — | 263,000 |
| Logic Elements | — | 4,160 |
| Embedded System Blocks (ESBs) | — | Yes (memory + dedicated logic) |
| User I/Os | — | 93 |
| PLLs | — | 4 |
| Package Type | — | 144-ball FBGA (13x13 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage Support | — | 1.8 V / 2.5 V / 3.3 V (multiVolt I/O) |
| Suhu Operasi | — | 0 °C to 85 °C (commercial) |
| Configuration Method | — | SRAM (volatile) - external boot PROM required |
| Boundary-Scan Support | — | IEEE 1149.1 (JTAG) |