EP20K100FC324-1V vs EP20K1000CF33I8N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K100FC324-1V disebabkan oleh Intel dan EP20K1000CF33I8N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP20K100FC324-1V | EP20K1000CF33I8N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Series | APEX-20K® | — |
| Number of Logic Elements / Cells | 4160 | 38,400 |
| Total RAM Bits | 53248 | — |
| Number of Gates (typical) | 100000 | — |
| Number of I/O | 252 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Supply Voltage - Core (VCCINT) | 2.375 V to 2.625 V | — |
| Supply Voltage - I/O (VCCIO) | 3.0 V / 3.3 V / 5.0 V tolerant (per I/O standard) | — |
| Speed Grade | -1V (commercial) | I8 |
| Suhu Operasi | 0C to +85C (commercial) | -40 °C to +85 °C (industrial) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Kemasan / Case | 324-FBGA (FineLine BGA, 19x19 mm) | — |
| Supplier Device Package | 324-FBGA | — |
| Number of PLLs | 4 | — |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL, GTL+, HSTL | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Programming Interface | JTAG (IEEE 1149.1) / in-system | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs status] |
| Family | — | APEX 20KC |
| Logic Elements | — | 38,400 cells |
| System Gates | — | 1,000,000 (approx.) |
| Maximum Internal Clock Frequency | — | 301.21 MHz |
| Propagation Delay | — | 1.79 ns |
| Process Technology | — | 0.15 µm CMOS |
| Core Supply Voltage | — | 1.8 V nominal (1.71 V to 1.89 V) |
| Number of I/O Pins | — | 700 user I/O |
| Bilangan Pin | — | 1020 |
| Package Type | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Embedded Memory | — | Dual-port RAM via ESB blocks |
| PLL Count | — | 4 |
| Configuration Interface | — | IEEE 1149.1 JTAG, EPC serial/parallel |