EP20K400CF672C7N vs EP20K400CF672C-8 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K400CF672C7N disebabkan oleh Altera dan EP20K400CF672C-8 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP20K400CF672C7N | EP20K400CF672C-8 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20K |
| Maximum System Gates | 1,052,000 | — |
| Typical Gates | 400,000 | 400,000 |
| Logic Elements (LEs) | 16,640 | — |
| Embedded Memory | 488 Kbits | — |
| Maximum User I/O | 488 | 488 |
| User I/O (per catalog) | 480 / 502 (per source) | — |
| Kemasan | 672-ball FineLine BGA (FC-FBGA / BBGA) | — |
| Process Technology | 0.18-micron CMOS, all-layer copper interconnect | 0.15 µm all-layer copper CMOS |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | 3.3 V / 2.5 V banked | [DATA_NEEDED: VCCIO options] |
| Propagation Delay | 2.5 ns (catalog) / 1.48 ns (some catalog) | — |
| Maximum Frequency | 375.94 MHz (internal) | — |
| Suhu Operasi | 0 C to 85 C (Commercial) | — |
| Jenis Pemasangan | Surface Mount (BGA) | Surface Mount (BGA) |
| Aras MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level] |
| Status RoHS | [DATA_NEEDED: RoHS status not in provided data] | [DATA_NEEDED: RoHS compliance] |
| Configuration Modes | PS, PPS, JTAG | — |
| Logic Elements | — | 16,640 |
| Macros | — | 1,664 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Speed Grade | — | -8 |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |