EP20K400EFC672-3N vs EP20K400EFI672-2N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K400EFC672-3N disebabkan oleh Intel dan EP20K400EFI672-2N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP20K400EFI672-2N - APEX-20K FPGA 16640 LEs 488 I/O FBGA-672 | Altera / Intel
EP20K400EFI672-2N ObsoletePengandingan Spesifikasi
| Parametr | EP20K400EFC672-3N | EP20K400EFI672-2N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | APEX 20KE | APEX-20K E |
| Series | APEX 20K | APEX-20K® |
| Device Type | FPGA - Field Programmable Gate Array | — |
| System Gates | 1,052,000 | — |
| Logic Elements | 16,640 | — |
| Logic Array Blocks (LABs) | 1,664 macros | — |
| Embedded RAM (EAB/ESB bits) | 212,992 bits | — |
| User I/O Pins | 488 | — |
| Kemasan | 672-BBGA (FC-FBGA) | — |
| Kiraan Pin | 672 | — |
| Propagation Delay | 2.5 ns | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| I/O Supply Voltage | 2.5 V | — |
| Suhu Operasi | 0 °C to +85 °C (commercial) | -40 °C to +100 °C (TJ) |
| Speed Grade | -3 | — |
| Technology | CMOS, 0.18 µm (per APEX 20KE family) | — |
| PLL Count | 4 | — |
| Architecture | MultiCore (LUT + Embedded System Blocks) | — |
| Status RoHS | [DATA_NEEDED: specific RoHS status - likely non-compliant given part age] | — |
| Manufacturer | — | Altera (now Intel Programmable Solutions Group) |
| Logic Elements / Cells | — | 16,640 |
| Number of LABs / CLBs | — | 1,664 |
| Total RAM Bits | — | 212,992 |
| Number of Gates (equivalent) | — | 1,052,000 |
| Number of I/O | — | 488 |
| Voltage - Supply (Core VCCINT) | — | 1.71 V to 1.89 V |
| Jenis Pemasangan | — | Surface Mount |
| Kemasan / Case | — | 672-BBGA, FCBGA |
| Supplier Device Package | — | 672-FBGA (27 x 27 mm) |
| Tingkat sensitiviti Air Nama (MSL) | — | 3 |
| Process Technology | — | CMOS |
| Configuration Method | — | Passive Serial / Active Serial / JTAG |