EP20K400GC655-2V vs EP20K400GC655-3X Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K400GC655-2V disebabkan oleh Altera dan EP20K400GC655-3X disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EP20K400GC655-2V | EP20K400GC655-3X |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Logic Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212,992 bits |
| System Gates | ~400,000 (typical marketing figure) | 400,000 |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | — |
| Process Technology | CMOS, 0.18 um | 0.22 µm CMOS |
| LVDS Support | Yes | — |
| Kemasan | 655-CPGA (62.48 x 62.48 mm) | — |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Jenis Pemasangan | Through-hole (CPGA) | Through-Hole (CPGA, ceramic) |
| Speed Grade | -2 | -3 (fastest) |
| Suhu Operasi | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: operating temperature range] |
| Status RoHS | unknown | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Logic Elements / Cells | — | 16,640 |
| Maximum Internal Frequency | — | 167 MHz (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| Kemasan / Case | — | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |