EP20K600CF33C7 vs EP20K600CF33C9 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K600CF33C7 disebabkan oleh Altera dan EP20K600CF33C9 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP20K600CF33C7 EP20K600CF33C9
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Series APEX-20K —
Family APEX-20K Field Programmable Gate Array APEX 20KC
Typical Gate Count 600,000 gates —
Logic Elements 24,320 —
Embedded RAM Bits 311,296 bits —
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count] —
Maximum User I/O Pins [DATA_NEEDED: max user I/O] —
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V 1.8 V nominal (1.71 V to 1.89 V)
I/O Supply Voltage (VCCIO) [DATA_NEEDED: VCCIO range] —
Gambaran Suhu Operasi -40C to +85C (Industrial) [DATA_NEEDED: operating temperature range]
Kemasan 1020-BBGA / FCBGA (33x33 mm) 1020-ball FC-FBGA
Package Code BGA, 1020 balls —
Speed Grade C7 (7 ns) —
Terminal Form Ball —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status]
Jenis Pemasangan Surface Mount Surface Mount (BGA)
Aras MSL [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL level]
Configuration Memory SRAM (volatile, requires external config device) —
Process Technology — 0.15 µm CMOS
System Gates — 600,000 (maximum)
Logic Elements / Cells — 24,320
Maximum Operating Frequency — 250 MHz
Frekuensi Klock Maksimum — 303.03 MHz
Propagation Delay — 2.0 ns
User I/O — 588 (4 dedicated inputs + 580 general-purpose I/O)
Embedded RAM — Dual-port RAM blocks (per family)
Programmability — JTAG / IEEE 1149.1 ISP, SRAM-based
Logic Block Architecture — MultiCore (LUT + product-term + embedded memory)
I/O Standards Supported — LVTTL, LVCMOS, LVDS (per family datasheet)

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