EP2C50F672I8N vs EP2C50F672C8 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP2C50F672I8N disebabkan oleh Altera dan EP2C50F672C8 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP2C50F672I8N | EP2C50F672C8 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Device Family | Cyclone II | — |
| Logic Technology | CMOS | — |
| Logic Elements | 50,528 | — |
| Embedded Memory | 594,432 bits | — |
| User I/O | 450 | — |
| Tegangan Pemberi Arus | 1.2 V | — |
| Package Type | 672-BGA | — |
| Package Designation | FBGA-672 | — |
| Kiraan Pin | 672 | — |
| Ordering Temperature Grade | I8N industrial grade designation | — |
| Jenis Pemasangan | Surface mount BGA | Surface Mount, BGA |
| Configuration Method | [DATA_NEEDED: configuration mode] | — |
| Gambaran Suhu Operasi | [DATA_NEEDED: operating temperature range] | — |
| Embedded Multipliers | [DATA_NEEDED: embedded multiplier count] | — |
| Phase-Locked Loops | [DATA_NEEDED: PLL count] | — |
| Global Clock Networks | [DATA_NEEDED: global clock network count] | 16 |
| Status RoHS | unknown | Compliant (lead-free FBGA) |
| REACH Status | unknown | — |
| Family | — | Cyclone II |
| Logic Elements (LE) | — | 50,528 |
| Configurable Logic Blocks (CLBs / LABs) | — | 3,158 |
| Embedded Memory (M4K blocks) | — | 594 Kbits (129 M4K blocks) |
| Embedded Multipliers (18x18) | — | 86 |
| Phase-Locked Loops (PLLs) | — | 4 |
| Maximum User I/O Pins | — | 450 |
| Process Technology | — | 90 nm CMOS, 1.2 V core |
| Maximum Internal Frequency | — | 402.58 MHz |
| Suhu Operasi | — | 0 °C to +85 °C (commercial) |
| Kemasan | — | 672-pin FBGA (FineLine BGA), 27 x 27 mm |
| Speed Grade | — | 8 |
| Configuration Mode | — | Active Serial (AS), Passive Serial (PS), JTAG, Fast Passive Parallel (FPP) |
| Aras MSL | — | 3 (168 hours) |