EP3SL50F484I4LN vs EP3SL50F484I4L Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP3SL50F484I4LN disebabkan oleh Altera dan EP3SL50F484I4L disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP3SL50F484I4LN EP3SL50F484I4L
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Product Type Field Programmable Gate Array (FPGA) —
Device Family Stratix III L —
Logic Cells 47,500 —
Embedded Memory 2,184,192 bits —
User I/O 296 —
Logic Array Blocks 1,900 LABs —
Listed Frequency 717 MHz —
Process Technology CMOS 65 nm low-power CMOS
Kemasan 484-BBGA, FCBGA 484-ball FBGA (FCBGA)
Package Description FBGA-484 —
Terminal Count 484 —
Terminal Form Ball —
Package Body Material Plastic/Epoxy —
Lead-Free Status Lead free —
Operating Temperature Grade Industrial —
I/O Banks [DATA_NEEDED: I/O bank count] —
Transceiver Count [DATA_NEEDED: transceiver count] —
Core Voltage [DATA_NEEDED: core voltage] —
I/O Voltage [DATA_NEEDED: I/O voltage] —
Junction Temperature [DATA_NEEDED: junction temperature] —
Status RoHS [DATA_NEEDED: RoHS status] —
REACH Status [DATA_NEEDED: REACH status] —
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 qualification] —
Series — Stratix III L (Low Power)
Family — Stratix III
Logic Elements (LE) — 47,500
Embedded Memory Bits — 2,184,192 bits (~273 KB)
User I/O Pins — 296
Speed Grade — 4
Suhu Operasi — 0 °C to 85 °C (commercial, per DigiKey listing)
Tegangan Pemberi Arus — 0.9 V core (family-typical)
Jenis Pemasangan — Surface Mount
Lead-Free / RoHS — Yes (RoHS compliant)
Configuration Modes — Passive Serial, Fast Passive Parallel, JTAG
Transceivers — Family supports up to 4 transceivers per family datasheet
DSP Blocks — Family supports up to 384 18x18 multipliers (family-level)

Laporan Datasheet & Sumber

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